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yosys/techlibs
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Eddie Hung 5ecbc6c7b2 Fix/cleanup +/xilinx/arith_map.v
2020-02-06 11:00:04 -08:00
..
achronix
anlogic Merge pull request #1604 from whitequark/unify-ram-naming 2020-01-02 21:06:17 +00:00
common Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux 2020-02-05 10:47:31 -08:00
coolrunner2
easic
ecp5 Add opt_lut_ins pass. (#1673) 2020-02-03 14:57:17 +01:00
efinix Merge pull request #1604 from whitequark/unify-ram-naming 2020-01-02 21:06:17 +00:00
gowin Add opt_lut_ins pass. (#1673) 2020-02-03 14:57:17 +01:00
greenpak4
ice40 Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards 2020-01-27 14:02:13 -08:00
intel Add log_experimental() and experimental() API and "yosys -x" 2020-01-27 18:27:47 +01:00
sf2
xilinx Fix/cleanup +/xilinx/arith_map.v 2020-02-06 11:00:04 -08:00
.gitignore