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ice40: reduce ABC9 internal fanout warnings with a param for CI->I3

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This commit is contained in:
Eddie Hung 2020-01-24 11:59:48 -08:00
parent da6abc0149
commit b178761551
6 changed files with 26 additions and 32 deletions
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4
techlibs/ice40/abc9_model.v
View file

@ -9,6 +9,8 @@ module \$__ICE40_CARRY_WRAPPER (
input I0, I3
);
parameter LUT = 0;
parameter I3_IS_CI = 0;
wire I3_OR_CI = I3_IS_CI ? CI : I3;
SB_CARRY carry (
.I0(A),
.I1(B),
@ -21,7 +23,7 @@ module \$__ICE40_CARRY_WRAPPER (
.I0(I0),
.I1(A),
.I2(B),
.I3(I3),
.I3(I3_OR_CI),
.O(O)
);
endmodule

3
techlibs/ice40/abc9_u.box
View file

@ -6,13 +6,12 @@
# Box 1 : $__ICE40_CARRY_WRAPPER (private cell used to preserve
# SB_LUT4+SB_CARRY)
# Outputs: O, CO
# (Exception: carry chain input/output must be the
# last input and output and the entire bus has been
# moved there overriding the otherwise
# alphabetical ordering)
# name ID w/b ins outs
$__ICE40_CARRY_WRAPPER 1 1 5 2
#A B I0 I3 CI
#A B I0 I3 CI
1231 1205 1285 874 874 # O
675 609 - - 278 # CO

5
techlibs/ice40/arith_map.v
View file

@ -49,13 +49,14 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
// A[1]: 1100 1100 1100 1100
// A[2]: 1111 0000 1111 0000
// A[3]: 1111 1111 0000 0000
.LUT(16'b 0110_1001_1001_0110)
.LUT(16'b 0110_1001_1001_0110),
.I3_IS_CI(1'b1)
) carry (
.A(AA[i]),
.B(BB[i]),
.CI(C[i]),
.I0(1'b0),
.I3(C[i]),
.I3(1'bx),
.CO(CO[i]),
.O(Y[i])
);

4
techlibs/ice40/ice40_opt.cc
View file

@ -139,7 +139,8 @@ static void run_ice40_opts(Module *module)
log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output));
cell->type = "$lut";
cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], cell->getPort("\\I3") });
auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3));
cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], I3 });
cell->setPort("\\Y", cell->getPort("\\O"));
cell->unsetPort("\\B");
cell->unsetPort("\\CI");
@ -148,6 +149,7 @@ static void run_ice40_opts(Module *module)
cell->unsetPort("\\CO");
cell->unsetPort("\\O");
cell->setParam("\\WIDTH", 4);
cell->unsetParam("\\I3_IS_CI");
}
continue;
}