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Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards

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Just like Verilog...
This commit is contained in:
Eddie Hung 2020-01-27 14:02:13 -08:00
parent cfb0366a18
commit e18aeda7ed
2 changed files with 2 additions and 2 deletions
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2
techlibs/ice40/ice40_opt.cc
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@ -140,7 +140,7 @@ static void run_ice40_opts(Module *module)
log_id(module), log_id(cell), log_signal(replacement_output));
cell->type = "$lut";
auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3)));
cell->setPort("\\A", { get_bit_or_zero(cell->getPort("\\I0")), inbit[0], inbit[1], I3 });
cell->setPort("\\A", { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort("\\I0")) });
cell->setPort("\\Y", cell->getPort("\\O"));
cell->unsetPort("\\B");
cell->unsetPort("\\CI");