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Code Activity
15145 commits 121 branches 59 tags 72 MiB
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2466 commits

Author SHA1 Message Date
Miodrag Milanovic
ee3162c58d Add PLL and EBR related primitives 2023-04-10 12:39:09 +02:00
gatecat
266f81816b ecp5: Remove TRELLIS_SLICE and add TRELLIS_COMB model 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-04-06 10:18:48 +01:00
Miodrag Milanovic
9e9fae1966 Add more DFF types 2023-04-06 09:10:14 +02:00
Miodrag Milanovic
d5a405d3b4 Added proper simulation model for CCU2D 2023-04-06 09:10:14 +02:00
Miodrag Milanovic
6e4c1675e7 Generate TRELLIS_DPR16X4 for lutram 2023-04-06 09:10:14 +02:00
Miodrag Milanovic
6e12da3956 machxo2: Initial support for carry chains (CCU2D) 2023-04-06 09:10:14 +02:00
Miodrag Milanovic
f35bdaa527 Update Xilinx cell definitions, fixes #3699 2023-03-23 09:44:36 +01:00
Miodrag Milanovic
ff9f1fb86e Start unification effort for machxo2 and ecp5 2023-03-20 09:58:41 +01:00
Miodrag Milanovic
4d7e9e2e5d Add additional iopad_external_pin attributes 2023-03-20 09:17:22 +01:00
Miodrag Milanovic
db367bd69e Add iopad_external_pin to some basic io primitives 2023-03-20 09:17:22 +01:00
Miodrag Milanovic
10589c57bf insert IO buffers for ECP5, off by default 2023-03-20 09:17:22 +01:00
Stefan Riesenberger
baa3659ea5 ice40: Fix path delay definitions 
Parallel connections do not allow matching different bit widths.
A full connection has to be used instead.
Allows iverilog to parse the simulation library with hardware path delays enabled.
 2023-03-10 10:48:05 +01:00
N. Engelhardt
1a3ff0d926
Merge pull request #3688 from pu-cc/gatemate-reginit 2023-03-01 09:49:14 +01:00
Miodrag Milanović
bb28e48136
Merge pull request #3663 from uis246/master 
gowin: Add new types of oscillator
 2023-02-28 06:56:01 +01:00
Miodrag Milanović
4ff9063145
Merge pull request #3652 from martell/elvds 
gowin: Add support for emulated differential output
 2023-02-28 06:55:25 +01:00
gatecat
2ab3747cc9 fabulous: Add support for mapping carry chains 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-02-27 09:50:34 +01:00
Oliver Keszöcze
fc56978703
Check DREG attribute 
The DSP48E1 implementation checked the wrong attribute (i.e. CREG) to initialize the D input register. This PR fixes 3680
 2023-02-17 17:54:41 +01:00
gatecat
25e7cb3bbb fabulous: Add CLK to BRAM interface primitives 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-02-16 12:55:53 +01:00
Patrick Urban
2c7ba0e752 gatemate: Enable register initialization 2023-02-15 17:29:01 +01:00
Patrick Urban
f37073050b gatemate: Update CC_PLL parameters 2023-02-14 12:02:41 +01:00
Patrick Urban
6a7d5257cd gatemate: Add CC_USR_RSTN primitive 2023-02-14 12:02:41 +01:00
Patrick Urban
4cb27b1a3a gatemate: Ensure compatibility of LVDS ports with VHDL 2023-02-14 12:02:41 +01:00
uis
ea6f562d49 gowin: Add new types of oscillator 2023-02-06 21:34:32 +00:00
martell
dbc8b77222 gowin: Add support for emulated differential output 2023-01-29 20:48:43 -08:00
Miodrag Milanović
611f71c670
Merge pull request #3630 from yrabbit/gw1n4c-pll 
gowin: add a new type of PLL - PLLVR
 2023-01-18 08:30:29 +01:00
Jannis Harder
5abaa59080
Merge pull request #3537 from jix/xprop 
New xprop pass
 2023-01-11 16:26:04 +01:00
YRabbit
d6a1e022e1 gowin: add a new type of PLL - PLLVR 
This primitive is used in the GW1NS-4, GW1NS-4C, GW1NSR-4, GW1NSR-4C and
GW1NSER-4C chips.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-01-11 11:41:29 +10:00
gatecat
7bac1920b2 nexus: Fix BRAM write enable in PDP mode 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-01-04 17:59:36 +01:00
Jannis Harder
7203ba7bc1 Add bitwise $bweqx and $bwmux cells 
The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`)
cells enable compact encoding and decoding of 3-valued logic signals
using multiple 2-valued signals.
 2022-11-30 18:24:35 +01:00
Jannis Harder
99163fb822 simlib: Use optional SIMLIB_GLOBAL_CLOCK to define a global clock signal 2022-11-30 18:24:35 +01:00
Jannis Harder
605d127517 simlib: Silence iverilog warning for $lut 
iverilog complains about implicitly truncating LUT when connecting it to
the `$bmux` A input. This explicitly truncates it to avoid that warning
without changing the behaviour otherwise.
 2022-11-30 18:24:35 +01:00
Jannis Harder
39ac113402 simlib: Fix wide $bmux and avoid iverilog warnings 2022-11-30 18:24:35 +01:00
Jannis Harder
b982ab4f59 satgen, simlib: Consistent x-propagation for $pmux cells 
This updates satgen and simlib to use a `$pmux` model where the output
is fully X when the S input is not all zero or one-hot with no x bits.
 2022-11-30 18:24:35 +01:00
gatecat
b6467f0801 fabulous: Allow adding extra custom prims and map rules 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-11-17 13:34:58 +01:00
gatecat
f111bbdf40 fabulous: improvements to the pass 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-11-17 13:34:58 +01:00
gatecat
e3f9ff2679 fabulous: Unify and update primitives 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-11-17 13:34:58 +01:00
TaoBi22
12c22045b7 Introduce RegFile mappings 2022-11-17 13:34:58 +01:00
TaoBi22
2b07e01ea4 Replace synth call with components, reintroduce flags and correct vpr flag implementation 2022-11-17 13:34:58 +01:00
TaoBi22
df56178567 Reorder operations to load in primitive library before hierarchy pass 2022-11-17 13:34:58 +01:00
TaoBi22
da32f21b59 Add plib flag to specify custom primitive library path 2022-11-17 13:34:58 +01:00
TaoBi22
950dde3081 Remove flattening from FABulous pass 2022-11-17 13:34:58 +01:00
TaoBi22
8fdf4948a8 Remove ALL currently unused flags (some to be reintroduced later and passed through to synth) 2022-11-17 13:34:58 +01:00
TaoBi22
2e9480be24 Add synth_fabulous ScriptPass 2022-11-17 13:34:58 +01:00
Jannis Harder
aa7e7df19f simlib: Simplify recently changed $mux model 
The use of a procedural continuous assignment introduced in #3526 was
unintended and is completely unnecessary for the actual change of that
PR.
 2022-10-28 19:48:00 +02:00
Jannis Harder
408fc60c95
Merge pull request #3526 from jix/mux-simlib-eval 
Consistent $mux undef handling
 2022-10-24 16:25:33 +02:00
Jannis Harder
c77b7343d0 Consistent $mux undef handling 
* Change simlib's $mux cell to use the ternary operator as $_MUX_
  already does
* Stop opt_expr -keepdc from changing S=x to S=0
* Change const eval of $mux and $pmux to match the updated simlib
  (fixes sim)
* The sat behavior of $mux already matches the updated simlib

The verilog frontend uses $mux for the ternary operators and this
changes all interpreations of the $mux cell (that I found) to match the
verilog simulation behavior for the ternary operator. For 'if' and
'case' expressions the frontend may also use $mux but uses $eqx if the
verilog simulation behavior is requested with the '-ifx' option.

For $pmux there is a remaining mismatch between the sat behavior and the
simlib behavior. Resolving this requires more discussion, as the $pmux
cell does not directly correspond to a specific verilog construct.
 2022-10-24 12:03:01 +02:00
Jannis Harder
0f96ae5990 Add smtmap.v describing the smt2 backend's behavior for undef bits 
Some builtin cells have an undefined (x) output even when all inputs are
defined. This is not natively supported by the formal backends which
will produce a fully defined value instead. This can lead to issues when
combining different backends in a formal flow. To work around these,
this adds a file containing verilog implementation of cells matching the
fully defined behavior implemented by the smt2 backend.
 2022-10-20 15:48:18 +02:00
Miodrag Milanovic
1ecf6aee9b Test fixes for latest iverilog 2022-09-21 15:46:43 +02:00
Tristan Gingold
1e0e3bd48e sf2: add NOTES about using yosys for smartfusion2 and igloo2 2022-08-31 08:40:44 +02:00
Tristan Gingold
0f6cf8b8e4 sf2: add a test for $alu gate 2022-08-31 08:40:44 +02:00