mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-07 01:54:10 +00:00
machxo2: Initial support for carry chains (CCU2D)
This commit is contained in:
parent
53c0a6b780
commit
6e12da3956
|
@ -9,3 +9,4 @@ $(eval $(call add_share_file,share/machxo2,techlibs/machxo2/lutrams.txt))
|
|||
$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/lutrams_map.v))
|
||||
$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/brams.txt))
|
||||
$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/brams_map.v))
|
||||
$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/arith_map.v))
|
||||
|
|
90
techlibs/machxo2/arith_map.v
Normal file
90
techlibs/machxo2/arith_map.v
Normal file
|
@ -0,0 +1,90 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
|
||||
* Copyright (C) 2018 gatecat <gatecat@ds0.me>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
(* techmap_celltype = "$alu" *)
|
||||
module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
|
||||
parameter A_SIGNED = 0;
|
||||
parameter B_SIGNED = 0;
|
||||
parameter A_WIDTH = 1;
|
||||
parameter B_WIDTH = 1;
|
||||
parameter Y_WIDTH = 1;
|
||||
|
||||
(* force_downto *)
|
||||
input [A_WIDTH-1:0] A;
|
||||
(* force_downto *)
|
||||
input [B_WIDTH-1:0] B;
|
||||
(* force_downto *)
|
||||
output [Y_WIDTH-1:0] X, Y;
|
||||
|
||||
input CI, BI;
|
||||
(* force_downto *)
|
||||
output [Y_WIDTH-1:0] CO;
|
||||
|
||||
wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
|
||||
|
||||
(* force_downto *)
|
||||
wire [Y_WIDTH-1:0] A_buf, B_buf;
|
||||
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
|
||||
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
|
||||
|
||||
function integer round_up2;
|
||||
input integer N;
|
||||
begin
|
||||
round_up2 = ((N + 1) / 2) * 2;
|
||||
end
|
||||
endfunction
|
||||
|
||||
localparam Y_WIDTH2 = round_up2(Y_WIDTH);
|
||||
|
||||
(* force_downto *)
|
||||
wire [Y_WIDTH2-1:0] AA = A_buf;
|
||||
(* force_downto *)
|
||||
wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;
|
||||
(* force_downto *)
|
||||
wire [Y_WIDTH2-1:0] BX = B_buf;
|
||||
(* force_downto *)
|
||||
wire [Y_WIDTH2-1:0] C = {CO, CI};
|
||||
(* force_downto *)
|
||||
wire [Y_WIDTH2-1:0] FCO, Y1;
|
||||
|
||||
genvar i;
|
||||
generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice
|
||||
CCU2D #(
|
||||
.INIT0(16'b0101_1010_1001_0110),
|
||||
.INIT1(16'b0101_1010_1001_0110),
|
||||
.INJECT1_0("NO"),
|
||||
.INJECT1_1("NO")
|
||||
) ccu2d_i (
|
||||
.CIN(C[i]),
|
||||
.A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b0),
|
||||
.A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b0),
|
||||
.S0(Y[i]), .S1(Y1[i]),
|
||||
.COUT(FCO[i])
|
||||
);
|
||||
|
||||
assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
|
||||
if (i+1 < Y_WIDTH) begin
|
||||
assign CO[i+1] = FCO[i];
|
||||
assign Y[i+1] = Y1[i];
|
||||
end
|
||||
end endgenerate
|
||||
|
||||
assign X = AA ^ BB;
|
||||
endmodule
|
|
@ -255,6 +255,26 @@ module DPR16X4C (
|
|||
assign DO = ram[RAD];
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
(* blackbox *)
|
||||
module CCU2D (
|
||||
CIN,
|
||||
A0, B0, C0, D0,
|
||||
A1, B1, C1, D1,
|
||||
S0, S1, COUT
|
||||
);
|
||||
|
||||
input CIN;
|
||||
input A0, B0, C0, D0;
|
||||
input A1, B1, C1, D1;
|
||||
output S0, S1, COUT;
|
||||
|
||||
parameter [15:0] INIT0 = 16'h0000;
|
||||
parameter [15:0] INIT1 = 16'h0000;
|
||||
parameter INJECT1_0 = "YES";
|
||||
parameter INJECT1_1 = "YES";
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module DP8KC(
|
||||
input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0,
|
||||
|
|
|
@ -69,6 +69,9 @@ struct SynthMachXO2Pass : public ScriptPass
|
|||
log(" -noiopad\n");
|
||||
log(" do not insert IO buffers\n");
|
||||
log("\n");
|
||||
log(" -ccu2\n");
|
||||
log(" use CCU2 cells in output netlist\n");
|
||||
log("\n");
|
||||
log(" -vpr\n");
|
||||
log(" generate an output netlist (and BLIF file) suitable for VPR\n");
|
||||
log(" (this feature is experimental and incomplete)\n");
|
||||
|
@ -80,7 +83,7 @@ struct SynthMachXO2Pass : public ScriptPass
|
|||
}
|
||||
|
||||
string top_opt, blif_file, edif_file, json_file;
|
||||
bool nobram, nolutram, flatten, vpr, noiopad;
|
||||
bool ccu2, nobram, nolutram, flatten, vpr, noiopad;
|
||||
|
||||
void clear_flags() override
|
||||
{
|
||||
|
@ -88,6 +91,7 @@ struct SynthMachXO2Pass : public ScriptPass
|
|||
blif_file = "";
|
||||
edif_file = "";
|
||||
json_file = "";
|
||||
ccu2 = false;
|
||||
nobram = false;
|
||||
nolutram = false;
|
||||
flatten = true;
|
||||
|
@ -147,6 +151,10 @@ struct SynthMachXO2Pass : public ScriptPass
|
|||
noiopad = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-ccu2") {
|
||||
ccu2 = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-vpr") {
|
||||
vpr = true;
|
||||
continue;
|
||||
|
@ -204,14 +212,17 @@ struct SynthMachXO2Pass : public ScriptPass
|
|||
|
||||
if (check_label("fine"))
|
||||
{
|
||||
run("opt -fast -mux_undef -undriven -fine");
|
||||
run("memory_map");
|
||||
run("opt -full");
|
||||
run("techmap -map +/techmap.v");
|
||||
run("opt -fast");
|
||||
run("opt -undriven -fine");
|
||||
}
|
||||
|
||||
if (check_label("map_ios", "(unless -noiopad)"))
|
||||
if (check_label("map_gates", "(unless -noiopad)"))
|
||||
{
|
||||
if (!ccu2)
|
||||
run("techmap");
|
||||
else
|
||||
run("techmap -map +/techmap.v -map +/machxo2/arith_map.v");
|
||||
if (!noiopad || help_mode)
|
||||
{
|
||||
run("iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad OBZ ~T:I:O -tinoutpad BB ~T:O:I:B A:top", "(only if '-iopad')");
|
||||
|
|
Loading…
Reference in a new issue