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0f96ae5990
Some builtin cells have an undefined (x) output even when all inputs are defined. This is not natively supported by the formal backends which will produce a fully defined value instead. This can lead to issues when combining different backends in a formal flow. To work around these, this adds a file containing verilog implementation of cells matching the fully defined behavior implemented by the smt2 backend. |
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| .. | ||
| achronix | ||
| anlogic | ||
| common | ||
| coolrunner2 | ||
| easic | ||
| ecp5 | ||
| efinix | ||
| gatemate | ||
| gowin | ||
| greenpak4 | ||
| ice40 | ||
| intel | ||
| intel_alm | ||
| machxo2 | ||
| nexus | ||
| quicklogic | ||
| sf2 | ||
| xilinx | ||
| .gitignore | ||