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yosys/techlibs
Jannis Harder 0f96ae5990 Add smtmap.v describing the smt2 backend's behavior for undef bits
Some builtin cells have an undefined (x) output even when all inputs are
defined. This is not natively supported by the formal backends which
will produce a fully defined value instead. This can lead to issues when
combining different backends in a formal flow. To work around these,
this adds a file containing verilog implementation of cells matching the
fully defined behavior implemented by the smt2 backend.
2022-10-20 15:48:18 +02:00
..
achronix Test fixes for latest iverilog 2022-09-21 15:46:43 +02:00
anlogic anlogic: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
common Add smtmap.v describing the smt2 backend's behavior for undef bits 2022-10-20 15:48:18 +02:00
coolrunner2 Blackbox all whiteboxes after synthesis 2021-03-17 21:07:20 +00:00
easic Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
ecp5 Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}. 2022-06-02 23:16:12 +02:00
efinix efinix: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
gatemate Fix static initialization, fixes mingw build 2022-07-04 19:31:38 +02:00
gowin Apicula now supports lutram 2022-07-03 12:45:03 +02:00
greenpak4 Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
ice40 Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
intel Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
intel_alm Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
machxo2 machxo2: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
nexus nexus: Fix BRAM mapping. 2022-08-09 23:47:55 +02:00
quicklogic Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
sf2 Test fixes for latest iverilog 2022-09-21 15:46:43 +02:00
xilinx Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00