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Code Activity
12887 commits 122 branches 59 tags 43 MiB
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1769 commits

Author SHA1 Message Date
Marcelina Kościelnicka
a4c04d1b90 ast: fix dump_vlog display of casex/casez 
The first child of AST_CASE is the case expression, it's subsequent
childrean that are AST_COND* and can be used to discriminate the type of
the case.
 2021-01-29 16:28:15 +01:00
Zachary Snow
27257a419f verilog: strip leading and trailing spaces in macro args 2021-01-28 11:26:35 -05:00
whitequark
ffbd813a8c
Merge pull request #2550 from zachjs/macro-arg-spaces 
verilog: allow spaces in macro arguments
 2021-01-25 10:36:07 +00:00
David Shah
09311b6581 dpi: Support for chandle type 
Signed-off-by: David Shah <dave@ds0.me>
 2021-01-23 22:24:31 +00:00
Henner Zeller
7d014902ec Fix digit-formatting calculation for small numbers. 
Calling log10() on zero causes a non-sensical value to be calculated. On some
compile options, I've observed yosys crashing with an illegal
instruction (SIGILL).

To make it safe, fix the calculation to do a range check; wrap it a
decimal_digits() function, and use it where the previous ceil(log10(n)) call
was used. As a side, it also improves readability.

Signed-off-by: Henner Zeller <h.zeller@acm.org>
 2021-01-21 12:20:53 -08:00
Zachary Snow
1096b969ef Allow combination of rand and const modifiers 2021-01-21 08:42:05 -07:00
Claire Xenia Wolf
acad7a6e40 Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavored Verific 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-01-20 20:48:10 +01:00
Zachary Snow
006c18fc11 sv: fix support wire and var data type modifiers 2021-01-20 09:16:21 -07:00
Zachary Snow
4fadcc8f25 verilog: allow spaces in macro arguments 2021-01-20 08:49:58 -07:00
Kamil Rakoczy
61501e3266 Fix input/output attributes when resolving typedef of wire 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2021-01-18 17:31:22 +01:00
Lukasz Dalek
09071afe15 Parse package user type in module port list 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2021-01-18 17:31:22 +01:00
Tom Verbeure
3a8eecebba Fix indents. 2021-01-04 00:17:16 -08:00
Tom Verbeure
bb3439562e Add -nosynthesis flag for read_verilog command. 2021-01-04 00:11:01 -08:00
whitequark
bc2de4567c
Merge pull request #2518 from zachjs/recursion 
verilog: improved support for recursive functions
 2021-01-01 09:32:26 +00:00
Zachary Snow
2085d9a55d verilog: improved support for recursive functions 2020-12-31 18:33:59 -07:00
Zachary Snow
75abd90829 sv: complete support for implied task/function port directions 2020-12-31 16:17:13 -07:00
Zachary Snow
750831e3e0 Fix elaboration of whole memory words used as indices 2020-12-26 21:47:38 -07:00
Zachary Snow
1419c8761c Fix constants bound to redeclared function args 
The changes in #2476 ensured that function inputs like `input x;`
retained their single-bit size when instantiated with a constant
argument and turned into a localparam. That change did not handle the
possibility for an input to be redeclared later on with an explicit
width, such as `integer x;`.
 2020-12-26 08:48:01 -07:00
whitequark
deff6a9546
Merge pull request #2501 from zachjs/genrtlil-tern-sign 
genrtlil: fix mux2rtlil generated wire signedness
 2020-12-23 23:15:56 +00:00
whitequark
8ef6b77dc3
Merge pull request #2476 from zachjs/const-arg-width 
Fix constants bound to single bit arguments (fixes #2383)
 2020-12-23 23:15:30 +00:00
Zachary Snow
999eec5617 genrtlil: fix mux2rtlil generated wire signedness 2020-12-22 17:49:16 -07:00
Zachary Snow
8206546c45 Fix constants bound to single bit arguments (fixes #2383) 2020-12-22 17:01:03 -07:00
whitequark
3e67ab1ebb
Merge pull request #2479 from zachjs/const-arg-hint 
Allow constant function calls in constant function arguments
 2020-12-22 01:31:25 +00:00
Zachary Snow
0d8e5d965f Sign extend port connections where necessary 
- Signed cell outputs are sign extended when bound to larger wires
- Signed connections are sign extended when bound to larger cell inputs
- Sign extension is performed in hierarchy and flatten phases
- genrtlil indirects signed constants through signed wires
- Other phases producing RTLIL may need to be updated to preserve
  signedness information
- Resolves #1418
- Resolves #2265
 2020-12-18 20:33:14 -07:00
Zachary Snow
186d6df4c3 Allow constant function calls in constant function arguments 2020-12-07 13:53:27 -07:00
whitequark
90724ea9e7
Merge pull request #2456 from Zottel/master 
Return correct modname when found in cache.
 2020-12-02 22:20:02 +00:00
Miodrag Milanovic
1c4a18f66f Bump required Verific version 2020-12-02 15:18:04 +01:00
georgerennie
c1f6ce8b33 Fix SYNTHESIS always being defined in Verilog frontend 2020-12-01 01:37:19 +00:00
Julius Roob
2e23dfd96b Return correct modname when found in cache. 2020-11-26 13:31:22 +01:00
whitequark
015b476e56 rtlil: remove dotted identifiers. 
No one knows where they came from and they never did anything useful.
 2020-11-25 16:47:20 +00:00
Miodrag Milanovic
c228cb74d6 Update verific version 2020-10-30 08:32:59 +01:00
Claire Xenia Wolf
acc9d0575b Fix argument handling in connect_rpc 
Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>
 2020-10-19 13:40:57 +02:00
Miodrag Milanovic
c8f052bbe0 extend verific library API for formal apps and generators 2020-10-12 14:56:15 +02:00
Miodrag Milanović
1b7ed719a5
Update required Verific version 2020-10-05 13:27:27 +02:00
Claire Xenia Wolf
46f0932c4c Ignore empty parameters in Verilog module instantiations 
Fixes #2394

Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>
 2020-10-01 18:27:16 +02:00
clairexen
7e2fc2eaeb
Merge pull request #2378 from udif/pr_dollar_high_low 
Added $high(), $low(), $left(), $right()
 2020-10-01 18:17:36 +02:00
Miodrag Milanovic
a44c5df259 use sha1 for parameter list in case if they contain spaces 2020-09-30 09:16:59 +02:00
Miodrag Milanovic
44705102b5 Better error for unsupported SVA sequence 2020-09-18 17:08:00 +02:00
clairexen
f176bd7778
Merge pull request #2329 from antmicro/arrays-fix-multirange-size 
Rewrite multirange arrays sizes [n] as [n-1:0]
 2020-09-17 18:27:05 +02:00
clairexen
9e937961dc
Merge pull request #2330 from antmicro/arrays-fix-multirange-access 
Fix unsupported subarray access detection
 2020-09-17 18:21:53 +02:00
Udi Finkelstein
7ed0e23e19 We can now handle array slices (e.g. $size(x[1]) etc. ) 2020-09-17 00:55:17 +03:00
Udi Finkelstein
6de7ba02e3 Fixed comments, removed debug message 2020-09-16 10:57:06 +03:00
Udi Finkelstein
b548722bee Added $high(), $low(), $left(), $right() 2020-09-15 20:49:52 +03:00
Miodrag Milanovic
3f27a4ea68 Use latest verific 2020-09-02 10:22:25 +02:00
clairexen
a10893072b
Merge pull request #2352 from zachjs/const-func-localparam 
Allow localparams in constant functions
 2020-09-01 17:31:48 +02:00
clairexen
c1a6097376
Merge pull request #2366 from zachjs/library-format 
Simple support for %l format specifier
 2020-09-01 17:30:36 +02:00
clairexen
3e1840d036
Merge pull request #2353 from zachjs/top-scope 
Module name scope support
 2020-09-01 17:30:09 +02:00
clairexen
452442ac2f
Merge pull request #2365 from zachjs/const-arg-loop-split-type 
Fix constant args used with function ports split across declarations
 2020-09-01 17:28:35 +02:00
Miodrag Milanovic
04d5692a85 Reorder to prevent crash 2020-08-31 12:22:26 +02:00
Miodrag Milanovic
3af499c60f ast recognize lower case x and z and verific gives upper case 2020-08-30 13:33:03 +02:00