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sv: complete support for implied task/function port directions

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This commit is contained in:
Zachary Snow 2020-12-31 16:14:35 -07:00
parent 48d0aeb094
commit 75abd90829
3 changed files with 39 additions and 0 deletions
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10
frontends/verilog/verilog_parser.y
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@ -884,7 +884,11 @@ task_func_args:
task_func_port:
attr wire_type range {
bool prev_was_input = true;
bool prev_was_output = false;
if (albuf) {
prev_was_input = astbuf1->is_input;
prev_was_output = astbuf1->is_output;
delete astbuf1;
if (astbuf2 != NULL)
delete astbuf2;
@ -893,6 +897,12 @@ task_func_port:
albuf = $1;
astbuf1 = $2;
astbuf2 = checkRange(astbuf1, $3);
if (!astbuf1->is_input && !astbuf1->is_output) {
if (!sv_mode)
frontend_verilog_yyerror("task/function argument direction missing");
astbuf1->is_input = prev_was_input;
astbuf1->is_output = prev_was_output;
}
} wire_name |
{
if (!astbuf1) {