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Allow combination of rand and const modifiers

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This commit is contained in:
Zachary Snow 2021-01-21 08:30:55 -07:00
parent 699a98b265
commit 1096b969ef
3 changed files with 19 additions and 2 deletions
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12
frontends/verilog/verilog_parser.y
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@ -651,8 +651,16 @@ wire_type_signedness:
%empty;
wire_type_const_rand:
TOK_CONST { current_wire_const = true; } |
TOK_RAND { current_wire_rand = true; } |
TOK_RAND TOK_CONST {
current_wire_rand = true;
current_wire_const = true;
} |
TOK_CONST {
current_wire_const = true;
} |
TOK_RAND {
current_wire_rand = true;
} |
%empty;
opt_wire_type_token: