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Merge pull request #2501 from zachjs/genrtlil-tern-sign

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genrtlil: fix mux2rtlil generated wire signedness
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whitequark 2020-12-23 23:15:56 +00:00 • committed by GitHub
commit deff6a9546
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2 changed files with 10 additions and 4 deletions
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frontends/ast/genrtlil.cc
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@ -141,6 +141,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size());
wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", that->filename.c_str(), that->location.first_line, that->location.first_column, that->location.last_line, that->location.last_column);
wire->is_signed = that->is_signed;
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)