Zachary Snow 0d8e5d965f Sign extend port connections where necessary ... - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265		2020-12-18 20:33:14 -07:00
..
aiger	Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().	2020-06-19 15:48:58 +00:00
ast	Sign extend port connections where necessary	2020-12-18 20:33:14 -07:00
blif	Use C++11 final/override keywords.	2020-06-18 23:34:52 +00:00
json	Use C++11 final/override keywords.	2020-06-18 23:34:52 +00:00
liberty	Use C++11 final/override keywords.	2020-06-18 23:34:52 +00:00
rpc	Fix argument handling in connect_rpc	2020-10-19 13:40:57 +02:00
rtlil	rtlil: remove dotted identifiers.	2020-11-25 16:47:20 +00:00
verific	Bump required Verific version	2020-12-02 15:18:04 +01:00
verilog	Fix SYNTHESIS always being defined in Verilog frontend	2020-12-01 01:37:19 +00:00