4237 commits

Author	SHA1	Message	Date
Akash Levy	03f76bbddd	Remove comments	2024-10-02 16:59:01 -07:00
Akash Levy	dd7e302aaa	Revert wreduce	2024-10-02 03:55:19 -07:00
Akash Levy	599cebfca5	Include pmuxtree	2024-09-29 05:31:51 -07:00
Akash Levy	49d948d873	Fix splitfanout: keep original cell, add new cells to driver db to fix net messup	2024-09-29 03:07:07 -07:00
Akash Levy	7f05f0b273	Fix muxadd peepopt to track bitsplit	2024-09-27 02:28:32 -07:00
Akash Levy	b1383a80cf	Make renaming nicer for bmuxmap -pmux	2024-09-27 00:54:05 -07:00
Akash Levy	dbaaf78044	Iterate to new wire	2024-09-24 16:47:35 -07:00
Akash Levy	ebf8783b4b	Fixup parameters	2024-09-24 13:55:09 -07:00
Akash Levy	9193b0e324	Merge branch 'YosysHQ:main' into main	2024-09-23 06:27:58 -07:00
N. Engelhardt	8e1e2b9a39	Merge pull request #4495 from povik/check-avert-costly-detail	2024-09-23 15:19:48 +02:00
Akash Levy	9f44ec8aa1	Merge branch 'YosysHQ:main' into main	2024-09-17 15:24:05 -07:00
Martin Povišer	38de01807e	Mark bufnorm experimental	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	80119386c0	Add RTLIL "buffered-normalized mode" and improve "bufnorm" pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	8bb70bac8d	Improvements in "bufnorm" pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	d027ead4b5	Improvements in "bufnorm" pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	f4b7ea5fb3	Improvements in "bufnorm" pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	32808a0393	Improvements and fixes to "bufnorm" cmd ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	d0b5dfa6ef	Add bufnorm pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Akash Levy	210ec6585f	Merge branch 'YosysHQ:main' into main	2024-09-16 06:59:25 -07:00
Emil J	52382c6544	Merge pull request #4583 from YosysHQ/emil/clock_gate ... clockgate: centralize clock enables out of FFs	2024-09-16 15:41:01 +02:00
Emil J. Tywoniak	f193bcf683	clockgate: help string	2024-09-16 14:20:33 +02:00
Emil J. Tywoniak	be7c93ec6d	clockgate: 1-bit const 0	2024-09-16 13:58:27 +02:00
Emil J	a8a92d3469	clockgate: help string ... Co-authored-by: Martin Povišer <povik@cutebit.org>	2024-09-16 13:55:53 +02:00
Akash Levy	285c8a3f66	Merge branch 'YosysHQ:main' into main	2024-09-12 11:14:15 -07:00
N. Engelhardt	c8b42b7d48	Merge pull request #4538 from RCoeurjoly/verific_bounds	2024-09-12 13:04:04 +02:00
Akash Levy	985de62d3c	Merge branch 'YosysHQ:main' into main	2024-09-11 16:01:37 -07:00
Emil J. Tywoniak	1e999a3cb7	clockgate: EN can be a bit on a multi-bit wire	2024-09-11 19:18:25 +02:00
Martin Povišer	34572708d5	Merge pull request #4595 from YosysHQ/emil/internal_stats-astnode ... internal_stats: astnode (sizeof)	2024-09-11 12:21:29 +02:00
Emil J. Tywoniak	1372c47036	internal_stats: astnode (sizeof)	2024-09-11 11:34:20 +02:00
Emil J. Tywoniak	8b464341c2	clockgate: no initvals	2024-09-11 10:24:48 +02:00
Roland Coeurjoly	bdc43c6592	Add left and right bound properties to wire. Add test. Fix printing ... for signed attributes Co-authored-by: N. Engelhardt <nak@yosyshq.com> Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>	2024-09-10 12:52:42 +02:00
Emil J. Tywoniak	7e473299bd	clockgate: bail on constant signals	2024-09-09 21:20:19 +02:00
Akash Levy	d427b78afd	Merge branch 'YosysHQ:main' into main	2024-09-09 10:16:51 -07:00
Emil J. Tywoniak	e64fceef70	clockgate: prototype clock gating	2024-09-09 15:00:54 +02:00
Hoa Nguyen	c1205ebc42	Initialize area stats in stat pass ... Currently, the area variables in the stat struct are not initialized. This caused the area stats occasionally being an erroneous value. Signed-off-by: Hoa Nguyen <hnpl@google.com>	2024-09-07 21:30:58 -07:00
Akash Levy	20c5ed2ebb	Merge latest	2024-09-06 07:43:14 -07:00
Miodrag Milanović	b20df72e1e	Merge pull request #4536 from YosysHQ/functional ... Functional Backend	2024-09-06 10:05:04 +02:00
Akash Levy	63a7996cb4	Merge branch 'YosysHQ:main' into main	2024-09-05 17:07:57 -07:00
Emil J. Tywoniak	14b9155492	internal_stats: fix doc build by adding a help string	2024-09-05 11:22:21 +02:00
Akash Levy	bebdb2f035	Reduce verbosity	2024-09-05 00:56:01 -07:00
Akash Levy	120f69eda7	Merge branch 'YosysHQ:main' into main	2024-09-04 00:02:25 -07:00
Martin Povišer	68fbca8769	Merge pull request #4554 from YosysHQ/emil/devstat ... internal_stats: init, report current memory consumption on linux and mac	2024-09-03 21:06:46 +02:00
Emil J. Tywoniak	0ce7631956	internal_stats: init, report current memory consumption on linux and mac	2024-09-03 19:28:24 +02:00
Akash Levy	2c9c6e693f	Add muxadd peepopt	2024-08-30 04:45:01 -07:00
Akash Levy	8f26fa9077	Fix for less pessimism in muxpack and opt_tree_balance	2024-08-29 23:44:57 -07:00
George Rennie	bdb5d45591	proc_dff: respect sync rule priorities when generating complex dffsrs ... * This fixes #4560, where previously the order that sync rules were processed in depended on the order they were pulled out of a std::map. This PR changes this to process them in the order they are found in, respecting the priorities among the async signals	2024-08-28 15:48:07 +01:00
Akash Levy	ab20bbbe8e	Fix bug	2024-08-27 23:23:49 -07:00
Akash Levy	401ffbd47e	Smallfix	2024-08-27 18:14:29 -07:00
Akash Levy	bbfdb460a5	Unclog the log	2024-08-27 18:13:43 -07:00
Akash Levy	11c05e2e40	Revert "Reapply "Reapply "Reapply "Add fanoutlimit"""" ... This reverts commit cf6c4ec6e4.	2024-08-27 17:38:48 -07:00