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Add muxadd peepopt

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This commit is contained in:
Akash Levy 2024-08-30 04:45:01 -07:00
parent 8f26fa9077
commit 2c9c6e693f
4 changed files with 47 additions and 0 deletions
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1
Makefile
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@ -716,6 +716,7 @@ OBJS += passes/cmds/clean_zerowidth.o
OBJS += passes/cmds/splitfanout.o
include $(YOSYS_SRC)/passes/memory/Makefile.inc
include $(YOSYS_SRC)/passes/pmgen/Makefile.inc
include $(YOSYS_SRC)/passes/proc/Makefile.inc
include $(YOSYS_SRC)/passes/opt/Makefile.inc

1
passes/pmgen/Makefile.inc
View file

@ -57,6 +57,7 @@ PEEPOPT_PATTERN = passes/pmgen/peepopt_shiftmul_right.pmg
PEEPOPT_PATTERN += passes/pmgen/peepopt_shiftmul_left.pmg
PEEPOPT_PATTERN += passes/pmgen/peepopt_shiftadd.pmg
PEEPOPT_PATTERN += passes/pmgen/peepopt_muldiv.pmg
PEEPOPT_PATTERN += passes/pmgen/peepopt_muxadd.pmg
passes/pmgen/peepopt_pm.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN)
$(P) mkdir -p passes/pmgen && $(PYTHON_EXECUTABLE) $< -o $@ -p peepopt $(filter-out $<,$^)

3
passes/pmgen/peepopt.cc
View file

@ -42,6 +42,8 @@ struct PeepoptPass : public Pass {
log("\n");
log("This pass employs the following rules:\n");
log("\n");
log(" * muxadd - Replace S?(A+B):A with A+(S?B:0)\n");
log("\n");
log(" * muldiv - Replace (A*B)/B with A\n");
log("\n");
log(" * shiftmul - Replace A>>(B*C) with A'>>(B<<K) where C and K are constants\n");
@ -90,6 +92,7 @@ struct PeepoptPass : public Pass {
pm.run_shiftmul_right();
pm.run_shiftmul_left();
pm.run_muldiv();
pm.run_muxadd();
}
}
}

42
passes/pmgen/peepopt_muxadd.pmg Normal file
View file

@ -0,0 +1,42 @@
pattern muxadd
//
// Transforms add->mux into mux->add:
// y = s ? (a + b) : a ===> y = a + (s ? b : 0)
//
state <SigSpec> add_y add_a add_b
match add
select add->type == $add
endmatch
code add_y add_a add_b
add_y = port(add, \Y);
add_a = port(add, \A);
add_b = port(add, \B);
branch;
std::swap(add_a, add_b);
endcode
match mux
select mux->type == $mux
index <SigSpec> port(mux, \A) === SigSpec({Const(State::S0, GetSize(add_y)-GetSize(add_a)), add_a})
index <SigSpec> port(mux, \B) === add_y
endmatch
code
SigSpec mux_y = port(mux, \Y);
SigSpec mid = module->addWire(NEW_ID, GetSize(add_b));
mux->setPort(\A, Const(State::S0, GetSize(add_b)));
mux->setPort(\B, add_b);
mux->setPort(\Y, mid);
add->setPort(\B, mid);
add->setPort(\Y, mux_y);
log("muxadd pattern in %s: mux=%s, add=%s\n", log_id(module), log_id(mux), log_id(add));
mux->fixup_parameters();
accept;
endcode