Roland Coeurjoly bdc43c6592 Add left and right bound properties to wire. Add test. Fix printing ... for signed attributes Co-authored-by: N. Engelhardt <nak@yosyshq.com> Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>		2024-09-10 12:52:42 +02:00
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cmds	Add left and right bound properties to wire. Add test. Fix printing	2024-09-10 12:52:42 +02:00
equiv	equiv_simple: Take FFs into account for driver map	2024-02-21 12:05:52 +01:00
fsm	add option to fsm_detect to ignore self-resetting	2023-01-30 16:12:53 +01:00
hierarchy	cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter	2024-07-29 10:26:02 +02:00
memory	memory_map: Explain -iattr better	2024-03-06 15:15:37 +01:00
opt	Merge pull request #4176 from povik/opt_expr-performance	2024-07-15 16:10:25 +02:00
pmgen	Merge pull request #4452 from phsauter/shiftadd-underflow-fix	2024-08-19 15:45:46 +02:00
proc	proc_rom: Set src on the emitted memory	2024-07-25 23:14:27 +01:00
sat	Set ranges on exported wires in VCD and FST	2024-08-02 15:23:00 +02:00
techmap	Improve libparse encapsulation	2024-08-13 18:47:36 +02:00
tests	cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter	2024-07-29 10:26:02 +02:00