mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

Iterate to new wire

Browse source
This commit is contained in:
Akash Levy 2024-09-24 16:47:35 -07:00
parent ebf8783b4b
commit dbaaf78044
1 changed files with 3 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/opt/wreduce.cc
View file

@ -458,7 +458,9 @@ struct WreduceWorker
continue;
log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), log_id(module), log_id(w));
Wire *nw = module->addWire(IdString("$" + w->name.str()), GetSize(w) - unused_top_bits);
IdString nw_name = IdString("$" + w->name.str());
while (module->count_id(nw_name)) nw_name = IdString("$" + nw_name.str());
Wire *nw = module->addWire(nw_name, GetSize(w) - unused_top_bits);
module->connect(nw, SigSpec(w).extract(0, GetSize(nw)));
module->swap_names(w, nw);
}