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https://github.com/YosysHQ/yosys
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Reduce verbosity
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parent
42dc3f6da6
commit
bebdb2f035
2 changed files with 7 additions and 7 deletions
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@ -80,7 +80,7 @@ struct SplitfanoutWorker
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outsig = conn.second;
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}
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if (output_count != 1) {
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log("Skipping %s cell %s/%s with %d output ports.\n", log_id(cell->type), log_id(module), log_id(cell), output_count);
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log_debug("Skipping %s cell %s/%s with %d output ports.\n", log_id(cell->type), log_id(module), log_id(cell), output_count);
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return 0;
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}
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@ -88,7 +88,7 @@ struct SplitfanoutWorker
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auto bit_users = bit_users_db[outsig[0]];
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for (int i = 0; i < GetSize(outsig); i++) {
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if (bit_users_db[outsig[i]] != bit_users) {
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log("Skipping %s cell %s/%s with bit-split output.\n", log_id(cell->type), log_id(module), log_id(cell));
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log_debug("Skipping %s cell %s/%s with bit-split output.\n", log_id(cell->type), log_id(module), log_id(cell));
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return 0;
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}
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}
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@ -98,7 +98,7 @@ struct SplitfanoutWorker
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return 0;
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// Iterate over bit users and create a new cell for each one
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log("Splitting %s cell %s/%s into %d copies based on fanout\n", log_id(cell->type), log_id(module), log_id(cell), GetSize(bit_users)-1);
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log_debug("Splitting %s cell %s/%s into %d copies based on fanout\n", log_id(cell->type), log_id(module), log_id(cell), GetSize(bit_users)-1);
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int foi = 0;
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cell->unsetPort(outport);
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for (auto bit_user : bit_users)
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@ -101,7 +101,7 @@ struct OptBalanceTreeWorker {
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void find_chain_start_cells() {
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for (auto cell : candidate_cells) {
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// Log candidate cell
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log("Considering %s (%s)\n", log_id(cell), log_id(cell->type));
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log_debug("Considering %s (%s)\n", log_id(cell), log_id(cell->type));
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// Get signals for cell ports
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SigSpec a_sig = sigmap(cell->getPort(ID::A));
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@ -172,7 +172,7 @@ struct OptBalanceTreeWorker {
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}
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cell->setPort(inport, inport_sig);
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cell->setParam(inport_width, GetSize(inport_sig));
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log("Width reduced %s/%s by %d bits\n", log_id(cell), log_id(inport), bits_removed);
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log_debug("Width reduced %s/%s by %d bits\n", log_id(cell), log_id(inport), bits_removed);
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}
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// Record number of bits removed from output
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@ -194,7 +194,7 @@ struct OptBalanceTreeWorker {
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}
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cell->setPort(ID::Y, y_sig);
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cell->setParam(ID::Y_WIDTH, GetSize(y_sig));
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log("Width reduced %s/Y by %d bits\n", log_id(cell), bits_removed);
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log_debug("Width reduced %s/Y by %d bits\n", log_id(cell), bits_removed);
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}
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}
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@ -207,7 +207,7 @@ struct OptBalanceTreeWorker {
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Cell *mid_cell = chain[GetSize(chain) / 2];
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Cell *midnext_cell = chain[GetSize(chain) / 2 + 1];
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Cell *end_cell = chain.back();
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log("Balancing chain of %d cells: mid=%s, midnext=%s, endcell=%s\n",
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log_debug("Balancing chain of %d cells: mid=%s, midnext=%s, endcell=%s\n",
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GetSize(chain), log_id(mid_cell), log_id(midnext_cell), log_id(end_cell));
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// Get mid signals
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