Miodrag Milanovic
169ffcd2fb
unify cycles counting and cleanup
2022-02-02 10:08:23 +01:00
Miodrag Milanovic
820b2fdd65
added stimulus mode and param check
2022-02-02 09:37:32 +01:00
Scott Thibault
0a6e2bd5d5
Update comment
2022-02-02 03:21:09 +01:00
Scott Thibault
e04ac4e9e9
Fix unextend method for signed constants
2022-02-02 03:21:09 +01:00
Miodrag Milanovic
8ba2000a50
error when no signal found
2022-01-31 17:41:50 +01:00
Miodrag Milanovic
1b5ff92e62
Cleanup
2022-01-31 13:45:28 +01:00
Miodrag Milanovic
eabd0ff115
Compare bits when not all are defined
2022-01-31 13:41:02 +01:00
Miodrag Milanovic
26de52fa09
Cleanup
2022-01-31 12:00:15 +01:00
Miodrag Milanovic
6513300db7
message update
2022-01-31 11:41:52 +01:00
Miodrag Milanovic
543feb75cb
Display simulation time data
2022-01-31 10:52:47 +01:00
Miodrag Milanovic
a6959d30df
Use edges when explicit
2022-01-31 09:38:25 +01:00
Miodrag Milanovic
cbadfa0268
Updating initial state and checks
2022-01-31 09:19:34 +01:00
Miodrag Milanovic
190e44f0da
Fix scope
2022-01-31 08:56:29 +01:00
Marcelina Kościelnicka
07a657fb0c
opt_reduce: Add $bmux and $demux optimization patterns.
2022-01-30 03:37:52 +01:00
Marcelina Kościelnicka
93508d58da
Add $bmux and $demux cells.
2022-01-28 23:34:41 +01:00
Miodrag Milanovic
f04d1398e5
check if stop before start
2022-01-28 19:41:43 +01:00
Miodrag Milanovic
ecbba625c4
set initial state, only flip-flops
2022-01-28 15:59:13 +01:00
Miodrag Milanovic
cb12b7c4d8
ignore not found private signals
2022-01-28 14:20:16 +01:00
Miodrag Milanovic
81b76155d6
recursive check
2022-01-28 13:24:38 +01:00
Miodrag Milanovic
4f75a2ca1b
Do actual compare
2022-01-28 12:50:41 +01:00
Miodrag Milanovic
3e35de2be1
Add more options and time handling
2022-01-28 10:18:02 +01:00
Marcelina Kościelnicka
db33b1e535
opt_dff: Don't mutate muxes while ModWalker is active.
2022-01-28 08:55:56 +01:00
Marcelina Kościelnicka
1759c80a3f
memory_bram: Make use of new mem emulation functions to map more RAMs.
2022-01-27 19:31:27 +01:00
Miodrag Milanovic
40018e191b
Display values of outputs
2022-01-26 16:52:36 +01:00
Miodrag Milanovic
be7be63fec
Check if stimulated
2022-01-26 15:51:43 +01:00
Miodrag Milanovic
9a8939f0a4
Read fst and use data to set inputs
2022-01-26 15:50:38 +01:00
Miodrag Milanovic
ccfc00705a
Add ability to write to FST file
2022-01-26 09:26:19 +01:00
Austin Seipp
b022fe61a7
opt_dff: fix sequence point copy paste bug
...
Newer GCCs emit the following warning for opt_dff:
passes/opt/opt_dff.cc:560:17: warning: operation on ‘ff.Yosys::FfData::has_clk’ may be undefined [-Wsequence-point]
560 | ff.has_clk = ff.has_ce = ff.has_clk = false;
| ~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Which is correct: the order of whether the read or write of has_clk
occurs first is undefined since there is no sequence point between them.
This is almost certainly just a typo/copy paste error and objectively
wrong, so just fix it.
Signed-off-by: Austin Seipp <aseipp@pobox.com>
2022-01-04 18:18:08 +01:00
Marcelina Kościelnicka
f84c9d8e17
memory_share: Fix SAT-based sharing for wide ports.
...
Fixes #3117 .
2021-12-20 18:40:14 +01:00
Catherine
4f1d62d9b2
bugpoint: avoid infinite loop between -connections and -wires.
...
Fixes #3113 .
2021-12-15 08:17:02 +00:00
Marcelina Kościelnicka
0aad88a2fb
Add clean_zerowidth pass, use it for Verilog output.
...
This should remove instances of zero-width sigspecs in the netlist,
avoiding problems in the Verilog backend with emitting them.
See #3103 .
2021-12-12 19:56:50 +01:00
Marcelina Kościelnicka
1184a7f3b4
opt_mem_priority: Fix non-ascii char in help message.
...
This is a fixed version of #3072 .
2021-12-09 00:56:14 +01:00
Lofty
77327b2544
sta: very crude static timing analysis pass
...
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
2021-11-25 17:20:27 +01:00
Marcelina Kościelnicka
107aad2cd2
show: Fix wire bit indexing.
...
Fixes #3078 .
2021-11-12 15:09:58 +01:00
Claire Xen
4699ddcc1b
Merge pull request #3077 from YosysHQ/claire/genlib
...
Add genlib support to ABC command
2021-11-10 20:02:34 +01:00
Claire Xen
c77d5a2aac
Spelling fix in abc.cc
2021-11-10 16:47:54 +01:00
Claire Xenia Wolf
093e287a1e
Add genlib support to ABC command
...
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-11-10 16:40:54 +01:00
Marcelina Kościelnicka
506acd52de
iopadmap: Fix ebmarassing typo
2021-11-10 14:56:03 +01:00
Marcelina Kościelnicka
15b0d717ed
iopadmap: Add native support for negative-polarity output enable.
2021-11-09 15:40:16 +01:00
Pepijn de Vos
0c7461fe5e
gowin: widelut support ( #3042 )
2021-11-06 16:09:30 +01:00
Miodrag Milanovic
d5de2a0cdb
Make it work on all
2021-11-05 10:51:58 +01:00
Miodrag Milanovic
cbb6887ac8
Correct way of setting maybe_unsused on labels
2021-11-05 10:36:15 +01:00
Marcelina Kościelnicka
f346868ccc
flatten: Keep sigmap around between flatten_cell invocations.
...
Fixes #3064 .
2021-11-02 13:18:15 +01:00
Marcelina Kościelnicka
8d881826eb
proc_dff: Emit $aldff.
2021-10-27 14:14:24 +02:00
Marcelina Kościelnicka
0a0df8d38c
dfflegalize: Refactor, add aldff support.
2021-10-27 14:14:01 +02:00
Zachary Snow
e833c6a418
verilog: use derived module info to elaborate cell connections
...
- Attempt to lookup a derived module if it potentially contains a port
connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
connections in a future change
2021-10-25 18:25:50 -07:00
Rupert Swarbrick
bd16d01c0e
Split out logic for reprocessing an AstModule
...
This will enable other features to use same core logic for replacing an
existing AstModule with a newly elaborated version.
2021-10-25 18:25:50 -07:00
Marcelina Kościelnicka
5cebf6a8ef
Change implicit conversions from bool to Sig* to explicit.
...
Also fixes some completely broken code in extract_reduce.
2021-10-21 20:20:31 +02:00
Marcelina Kościelnicka
e64456f920
extract_reduce: Refactor and fix input signal construction.
...
Fixes #3047 .
2021-10-21 04:10:01 +02:00
Paul Annesley
3efc14f5ad
dfflegalize: remove redundant check for initialized dlatch
...
This if condition is repeated verbatim, and I can't imagine a legitimate
way the inputs could change in between. I imagine it's a copy/paste
mistake.
2021-10-17 22:10:37 +02:00
