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verilog: use derived module info to elaborate cell connections

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- Attempt to lookup a derived module if it potentially contains a port
  connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
  connections in a future change
This commit is contained in:
Zachary Snow 2021-10-19 18:46:26 -06:00 • committed by Zachary Snow
parent bd16d01c0e
commit e833c6a418
15 changed files with 397 additions and 42 deletions
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4
passes/hierarchy/hierarchy.cc
View file

@ -558,6 +558,10 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
return did_something;
}
// Now that modules have been derived, we may want to reprocess this
// module given the additional available context.
if (module->reprocess_if_necessary(design))
return true;
for (auto &it : array_cells)
{

4
passes/techmap/techmap.cc
View file

@ -377,10 +377,12 @@ struct TechmapWorker
if (c->attributes.count(ID::src))
c->add_strpool_attribute(ID::src, extra_src_attrs);
if (techmap_replace_cell)
if (techmap_replace_cell) {
for (auto attr : cell->attributes)
if (!c->attributes.count(attr.first))
c->attributes[attr.first] = attr.second;
c->attributes.erase(ID::reprocess_after);
}
}
for (auto &it : tpl->connections()) {