3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 00:55:32 +00:00
Commit graph

3683 commits

Author SHA1 Message Date
Rupert Swarbrick
7746bba69a Simplify a modport check in hierarchy.cc
This code originally comes from commit 458a940. When an interface is
used via a modport, code in genrtlil.cc sets '\\interface_type' and
'\\interface_modport' properties on the wire.

In hierarchy.cc, we pick up the modport name and add it to a dict
called modports_used_in_submodule (that maps connection source to
modport name).

Before this patch, the modport name is retrieved as a strpool and then
iterated over in an arbitrary order, discarding all entries but the
last. In practice, the pool will always have 0 or 1 entries because
the string used to construct it is a valid identifier, so doesn't
contain any pipe symbols.

This patch changes the code to retrieve the modport name as just a
string. This will have the same effect in practice, but may be a bit
less confusing!

The code also gets moved down closer to where the result is used,
which might be a bit more efficient since we won't always get as far
as the check.

The patch also removes some commented-out code, which I think was
intended to add some typechecking at some point, but was never
implemented. Since this dates back to October 2018, I think it makes
more sense to just take it out.
2020-05-26 16:50:42 +01:00
Eddie Hung
00c5ceb1f2 abc9_ops: -prep_xaiger exclude (* abc9_keep *) wires from toposort 2020-05-25 16:40:53 -07:00
Alberto Gonzalez
9847a4eea8
smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4. 2020-05-25 20:39:30 +00:00
Alberto Gonzalez
f9eef5e3f7
qbfsat: Add support for CVC4. 2020-05-25 20:39:03 +00:00
Alberto Gonzalez
903456c267
qbfsat: Add -solver option and allow choice of Z3 or Yices, making Yices the default.
Ensures that "BV" is the logic whenever solving an exists-forall problem with Yices, moves the "(set-logic ...)" directive above any non-info line, sets the `ef-max-iters` parameter to a very high number when using Yices in exists-forall mode so as not to prematurely abandon difficult problems, and does not provide the incompatible "--incremental" Yices argument when in exists-forall mode.
2020-05-25 20:38:29 +00:00
Eddie Hung
721283ac2a blackbox: re-use existing Module::makeblackbox() method 2020-05-25 10:53:49 -07:00
Eddie Hung
7bad23f19c abc9_ops: -reintegrate to preserve flop names 2020-05-25 08:43:33 -07:00
clairexen
ae11156c90
Merge pull request #2015 from boqwxp/qbfsat-bisection
qbfsat: Add an iterative bisection optimization method and make it the default.
2020-05-25 15:50:18 +02:00
Alberto Gonzalez
ac41f8a9c7
qbfsat: Remove cruft inadvertently left untouched in commit 86fc49a9d6. 2020-05-23 00:53:09 +00:00
Alberto Gonzalez
aea0fd5ed4
qbfsat: Add bisection mode and make it the default.
Also adds `-nooptimize` and reorganizes `qbfsat.cc` a bit.
2020-05-23 00:53:09 +00:00
Eddie Hung
4f0f321169 abc9_ops: update comment 2020-05-21 21:39:13 -07:00
Miodrag Milanović
637650597b
Merge pull request #2059 from boqwxp/logger-vector-to-dict
log: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, warning, log}` to better express the intent that each element is unique.
2020-05-21 15:36:30 +02:00
Eddie Hung
2d573a0ff6
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff
abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
2020-05-18 08:06:50 -07:00
Alberto Gonzalez
8297afe925
log: Use dict instead of std::vector<std::pair> for log_expect_{error, warning, log} to better express the intent that each element is unique. 2020-05-15 00:55:32 +00:00
Eddie Hung
67fc0c3698 abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_
instead of moving them to $__ prefix
2020-05-14 16:44:35 -07:00
Eddie Hung
07eecff9cc
Merge pull request #2055 from YosysHQ/eddie/logger_multiple
logger: fix for multiple calls with same pattern
2020-05-14 15:30:08 -07:00
Alberto Gonzalez
e173291649
techmap: Replace naughty const_cast<>()s.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:55 +00:00
Alberto Gonzalez
97fd304cbe
techmap: Replace pseudo-private member usage with the range accessor function and some naughty const_cast<>()s. 2020-05-14 20:06:55 +00:00
Eddie Hung
36bb201dd9
techmap: sort celltypeMap as it determines techmap order 2020-05-14 20:06:55 +00:00
Alberto Gonzalez
ce62d0751a
Replace std::sets using custom comparators with pool.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:55 +00:00
Eddie Hung
dabeb1e8a1
techmap: prefix special wires with backslash for use as IdString 2020-05-14 20:06:55 +00:00
Alberto Gonzalez
bd54d67ad4
Further clean up passes/techmap/techmap.cc.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
982562ff13
Use emplace() for more efficient insertion into various dicts. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez
c658d9d59d
Build constant bits directly rather than constructing an object and copying its bits. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez
f235f212ea
Replace std::set with pool for cell_to_inbit and outbit_to_cell. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez
6294621825
Use emplace() rather than insert(). 2020-05-14 20:06:54 +00:00
Alberto Gonzalez
dfcb936cd5
Clean up pseudo-private member usage and ensure range iteration uses references where possible to avoid unnecessary copies. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez
a4755c50c3
Clean up extraneous buffer. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez
7857782575
Replace std::map with dict for unique_bit_id. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez
6d64d768b0
Replace std::map with dict for port_new2old_map, port_connmap, and cellbits_to_tplbits. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez
5cb4ae4666
Replace std::map with dict for connbits_map, cell_to_inbit, and outbit_to_cell. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez
c43017fc08
Replace std::map with dict for TechmapWires type. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez
644e55b3d3
Replace std::map with dict for celltypeMap. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez
67f4046c05
Replace std::set with pool for handled_cells and techmap_wire_names. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez
64c16f8c13
Replace std::map with dict for positional_ports. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez
2fb4931e5b
Add specialized hash() for type dict and use a dict instead of a std::map for techmap_cache and techmap_do_cache. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez
437f3fb342
Replace std::map with dict for simplemap_mappers. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez
99b586b283
Use nullptr instead of NULL in passes/techmap/techmap.cc. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez
5f7f213c7f
Replace std::string and RTLIL::IdString with IdString in passes/techmap/techmap.cc.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:53 +00:00
Alberto Gonzalez
e49fdee404
Do not modify design modules while iterating over modules().
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:53 +00:00
Alberto Gonzalez
985a29ff3b
Clean up pseudo-private member usage, superfluous std::vector instantiation, and RTLIL::id2cstr() usage in passes/techmap/techmap.cc. 2020-05-14 20:06:53 +00:00
Eddie Hung
7b3a4a1fff opt_expr: Sx to Sz; spotted by @Xiretza 2020-05-14 12:14:23 -07:00
Eddie Hung
73b7ea713c
Merge pull request #1994 from YosysHQ/eddie/fix_bug1758
opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too
2020-05-14 11:56:22 -07:00
Eddie Hung
425867d175 logger: clean up doc 2020-05-14 10:38:31 -07:00
Eddie Hung
02df0198b6 abc9_ops: -prep_hier to create unmap module that removes Q's (* init *) 2020-05-14 10:33:57 -07:00
Eddie Hung
13f9d65b6f abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it 2020-05-14 10:33:57 -07:00
Eddie Hung
fa31e84112 Fix broken test when ignoring abc9_flop with init == 1'b1 2020-05-14 10:33:57 -07:00
Eddie Hung
97a0a04314 abc9_ops/xaiger: further reducing Module::derive() calls by ...
replacing _all_ (* abc9_box *) instantiations with their derived types
2020-05-14 10:33:57 -07:00
Eddie Hung
e79127fceb Cleanup; reduce Module::derive() calls 2020-05-14 10:33:57 -07:00
Eddie Hung
8d34aee3d5 abc9: update to =_$abc9_flops pattern which includes whiteboxes 2020-05-14 10:33:57 -07:00