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abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_

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instead of moving them to $__ prefix
This commit is contained in:
Eddie Hung 2020-05-14 16:44:35 -07:00
parent 02df0198b6
commit 67fc0c3698
5 changed files with 11 additions and 23 deletions
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6
passes/techmap/abc9_ops.cc
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@ -563,7 +563,7 @@ void mark_scc(RTLIL::Module *module)
if (c.second.is_fully_const()) continue;
if (cell->output(c.first)) {
Wire *w = module->addWire(NEW_ID, GetSize(c.second));
w->set_bool_attribute(ID::abc9_scc);
w->set_bool_attribute(ID::abc9_keep);
module->connect(w, c.second);
c.second = w;
}
@ -1154,7 +1154,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
// Short out $_DFF_[NP]_ cells since the flop box already has
// all the information we need to reconstruct cell
if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) {
if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep)) {
module->connect(cell->getPort(ID::Q), cell->getPort(ID::D));
module->remove(cell);
}
@ -1373,7 +1373,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
RTLIL::Wire *mapped_wire = mapped_mod->wire(port);
RTLIL::Wire *wire = module->wire(port);
log_assert(wire);
wire->attributes.erase(ID::abc9_scc);
wire->attributes.erase(ID::abc9_keep);
RTLIL::Wire *remap_wire = module->wire(remap_name(port));
RTLIL::SigSpec signal(wire, remap_wire->start_offset-wire->start_offset, GetSize(remap_wire));