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1432 commits

Author SHA1 Message Date
Rasmus Munk Larsen
a6247cba42 Fix compiler warnings from GCC. 2023-10-03 09:29:06 +01:00
Rasmus Munk Larsen
cb9f318d37 Remove local modifications. 2023-10-03 09:29:06 +01:00
Rasmus Munk Larsen
ff915d21b6 Update comment. 2023-10-03 09:29:06 +01:00
Rasmus Munk Larsen
4968229efc Speed up stringf / vstringf by 1.8x.
The main speedup is accomplished by avoiding a heap allocation in the common case where the final string length is less than 128. Inlining stringf & vstringf adds an additional improvement.
2023-10-03 09:29:06 +01:00
Rasmus Munk Larsen
058973faee Undo formatting change. 2023-10-02 16:15:47 -07:00
Rasmus Munk Larsen
bce984fa60 Speed up OptMergePass by 1.7x.
The main speedup comes from swithing from using a SHA1 hash to std::hash<std::string>. There is no need to use an expensive cryptographic hash for fingerprinting in this context.
2023-10-02 15:57:18 -07:00
Martin Povišer
b894abf8b1
Merge pull request #3959 from rmlarsen/decode_string
Speed up RTLIL::Const::decode_string by 1.7x.
2023-10-02 16:38:43 +02:00
N. Engelhardt
dcb600ab81
Merge pull request #3938 from povik/booth-cleanup 2023-10-02 16:10:17 +02:00
Rasmus Munk Larsen
12218a4c74 Unflip i and j. 2023-09-28 19:39:09 -07:00
Rasmus Munk Larsen
01a015747e Speed up RTLIL::Const::decode_string by 1.7x. 2023-09-27 17:16:13 -07:00
Wanda
c172fef01a hashlib: Use a better hash for pool. 2023-09-26 18:55:06 +01:00
Martin Povišer
d641dfaec2 rtlil: Add helper to emit full-adder cells 2023-09-25 14:50:41 +02:00
Ethan Mahintorabi
aa06809d64 rtlil: Speeds up Yosys by 17%
This PR speeds up by roughly 17% across a wide spectrum of designs
tested at Google. Particularly for the mux generation pass.

Co-authored-by: Rasmus Larsen <rmlarsen@google.com>
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2023-09-21 10:46:11 +01:00
Rasmus Munk Larsen
b9745f638b Remove extraneous "public:". 2023-09-20 16:20:08 -07:00
Rasmus Munk Larsen
e0042bdff7 Speed up TopoSort. The main sorting algorithm implementation in TopoSort::sort_worker is 11-12x faster. Overall, the complete sequence of building the graph and sorting is about 2.5-3x faster. The overall impact in e.g. the replace_const_cells optimization pass is a ~25% speedup. End-to-end impact on our synthesis flow is about 3%. 2023-09-20 15:49:05 -07:00
Krystine Sherwin
98d0e749d6
Merge updates from 'master' into krys/docs 2023-09-19 11:28:36 +12:00
Jannis Harder
62b4df4989 dft_tag: Implement $overwrite_tag and $original_tag
This does not correctly handle an `$overwrite_tag` on a module output,
but since we currently require the user to flatten the design for
cross-module dft, this cannot be observed from within the design, only
by manually inspecting the signals in the design.
2023-09-13 11:32:36 +02:00
Miodrag Milanovic
27ac912709 Support import of $future_ff 2023-09-13 11:32:36 +02:00
Miodrag Milanovic
54050a8c16 Basic support for tag primitives 2023-09-13 11:32:36 +02:00
Martin Povišer
05f0262d77
Merge pull request #3929 from YosysHQ/gatecat/fmt-fix
fmt: Fix C++ string assertion when buf is empty
2023-09-12 19:44:17 +02:00
gatecat
98b9459535 fmt: Fix C++ string assertion when buf is empty
Signed-off-by: gatecat <gatecat@ds0.me>
2023-09-12 18:12:07 +02:00
Martin Povišer
cbc4ec8178 mem: Fix index confusion in write port merging
Fix mistaking the read-port and write-port indices for each other when
we are adding the partial transparency emulation to be able to merge two
write ports.
2023-09-12 16:43:59 +02:00
Martin Povišer
6d9cd16fad cellaigs: Drop initializer list in call to IdString::in
Remove superfluous curly braces in call to IdString::in to address
a compilation error (reproduced below) under GCC 9 and earlier.

kernel/cellaigs.cc:395:18: error: call to member function 'in' is ambiguous
if (cell->type.in({ID($gt), ID($ge)}))
~~~~~~~~~~~^~
./kernel/rtlil.h:383:8: note: candidate function
bool in(const std::string &rhs) const { return *this == rhs; }
^
./kernel/rtlil.h:384:8: note: candidate function
bool in(const pool &rhs) const { return rhs.co...
^
2023-08-14 11:42:19 +02:00
Charlotte
f9d38253c5 ast: add PRIORITY to $print cells 2023-08-11 04:46:52 +02:00
Charlotte
7f7c61c9f0 fmt: remove lzero by lowering during Verilog parse
See https://github.com/YosysHQ/yosys/pull/3721#issuecomment-1502037466
-- this reduces logic within the cell, and makes the rules that apply
much more clear.
2023-08-11 04:46:52 +02:00
Charlotte
3571bf2c2d fmt: fuzz, remove some unnecessary busywork
Removing some signed checks and logic where we've already guaranteed the
values to be positive.  Indeed, in these cases, if a negative value got
through (per my realisation in the signed fuzz harness), it would cause
an infinite loop due to flooring division.
2023-08-11 04:46:52 +02:00
Charlotte
9f9561379b fmt: format %t consistently at initial 2023-08-11 04:46:52 +02:00
Charlotte
75b44f21d1 fmt: rudimentary %m support (= %l) 2023-08-11 04:46:52 +02:00
Charlotte
c382d7d3ac fmt: %t/$time support 2023-08-11 04:46:52 +02:00
Charlotte
b0f69f2cd5 tests: test cxxrtl against iverilog (and uncover bug!) 2023-08-11 04:46:52 +02:00
Charlotte
095b093f4a cxxrtl: first pass of $print impl 2023-08-11 04:46:52 +02:00
Charlotte
d9e4582558 fmt: handle part with unspecified padding in emit_rtlil
e.g. `$displayh(8'ha)` won't have a padding set, because it just gets
`lzero` set instead by `compute_required_decimal_places`.

It also doesn't have a width.  In this case, we can just fill in a dummy
(unused) padding.  Either space or zero would work, but space is a bit
more distinct given the width field follows.

Also omit writing the width if it's zero.  This makes the emitted ilang
a little cleaner in places; `{8:> h0u}` is the output for this example,
now.  The other possible extreme would be `{8:>00h0u}`.
2023-08-11 04:46:52 +02:00
Charlotte
1a222cb163 fmt: function name typo 2023-08-11 04:46:52 +02:00
Charlotte
289f8d42cb fmt: correct parsing of {{ and }} for brace literals 2023-08-11 04:46:52 +02:00
Charlotte
3c8f84b70b fmt: fix another overrun 2023-08-11 04:46:52 +02:00
Charlotte
28bd3a4b5d fmt: don't overrun fmt string buffer
For input like "{", "{1", etc., we would exit the loop due to
`i < fmt.size()` no longer being the case, and then check if
`++i == fmt.size()`.  That would increment i to `fmt.size() + 1`,
and so execution continues.

The intention is to move i beyond the ':', so we do it only in that
case instead.
2023-08-11 04:46:52 +02:00
Charlotte
9db73aa872 celltypes: add $print
Otherwise, the \TRG connection is pruned by CleanZeroWidthPass.
2023-08-11 04:46:52 +02:00
whitequark
d5c9953c09 ast: translate $display/$write tasks in always blocks to new $print cell. 2023-08-11 04:46:52 +02:00
whitequark
9ea241711e kernel: add format string helpers, fmt. 2023-08-11 04:46:52 +02:00
Krystine Sherwin
8203a01ba9
Adding custom domain for cmdref 2023-08-08 11:51:57 +12:00
Jannis Harder
0a3f805daa
Merge pull request #3840 from povik/cellaigs-cmp-cells 2023-07-31 16:23:39 +02:00
dragonmux
ef7e358576
kernel/rtlil: Trailing whitespace cleanup 2023-07-26 20:50:55 +01:00
dragonmux
b59c717245
kernel/rtlil: Fixed the destruction guard for IdString
The guard is optimised out on some compilers under certain conditions (eg: LTO on GCC) as constant under C++ lifetime rules.
This is because the guard type's member is invalid to access (UB) after the type has been destroyed, resulting in
`destruct_guard.ok` being unable to be `false` according to the optimiser, based on the lifetime rules.

This patch still invokes UB (all accesses to the destroyed IdString instance are), but at least the optimiser
can't reason that destruct_guard_ok cannot be false and therefore it's safe to optimise out from its guard role.
2023-07-26 20:46:56 +01:00
Martin Povišer
3ec00cceaa cellaigs: Generate models for integer comparison cells
Add the case of $lt, $le, $gt, $ge to the code generating AIGs.
2023-07-25 11:45:18 +02:00
N. Engelhardt
5e8db7000c
Merge pull request #3839 from povik/python-log-newline 2023-07-24 16:28:02 +02:00
N. Engelhardt
43780c9812
Merge pull request #3838 from povik/various-cleanup 2023-07-24 16:24:23 +02:00
N. Engelhardt
2bc0d86de7
Merge pull request #3854 from povik/abits-wide_log2-assert 2023-07-24 16:20:51 +02:00
Martin Povišer
77d4b5230e ast: Move to a new helper method to print input errors
It's a repeating pattern to print an error message tied to an AST
node. Start using an 'input_error' helper for that. Among other
things this is beneficial in shortening the print lines, which tend
to be long.
2023-07-20 23:40:19 -04:00
Martin Povišer
6a553568c5 kernel/mem: Assert ABITS is not below wide_log2
Later in the check() code we check the bottom wide_log2 bits on the
address port are zeroed out. If the address port is too narrow, we crash
due to out of bounds access. Explicitly assert the address port is wide
enough, so we don't crash on input such as

    read_rtlil <<EOF
    module \top
      wire input 1 \clk

      memory width 8 size 2 \mem

      cell $memwr $auto$:1:$8
        parameter \PRIORITY 1'0
        parameter \CLK_POLARITY 1'1
        parameter \CLK_ENABLE 1'1
        parameter \MEMID "\\mem"
        parameter \ABITS 1'0
        parameter \WIDTH 6'010000
        connect \DATA 16'0000000000000000
        connect \ADDR { }
        connect \EN 16'0000000000000000
        connect \CLK \clk
      end
    end
    EOF
    memory
2023-07-19 16:50:59 +02:00
Martin Povišer
5584ce95db log: Detect newlines in Python log output
So that Python messages are annotated with timestamps too (if -t was
passed).
2023-07-10 13:19:20 +02:00