3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 17:15:33 +00:00

tests: test cxxrtl against iverilog (and uncover bug!)

This commit is contained in:
Charlotte 2023-06-28 11:51:18 +10:00 committed by Marcelina Kościelnicka
parent 095b093f4a
commit b0f69f2cd5
5 changed files with 276 additions and 1 deletions

View file

@ -45,7 +45,7 @@ struct VerilogFmtArg {
};
// RTLIL format part, such as the substitutions in:
// "foo {4: 4du} bar {2:01xs}"
// "foo {4:> 4du} bar {2:<01hs}"
struct FmtPart {
enum {
STRING = 0,