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https://github.com/YosysHQ/yosys
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kernel: add format string helpers, fmt.
This commit is contained in:
whitequark
Marcelina Kościelnicka
parent
f8e2c955fc
commit
9ea241711e
3 changed files with 673 additions and 6 deletions
577
kernel/fmt.cc
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577
kernel/fmt.cc
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@ -0,0 +1,577 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2020 whitequark <whitequark@whitequark.org>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "libs/bigint/BigUnsigned.hh"
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#include "kernel/fmt.h"
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USING_YOSYS_NAMESPACE
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void Fmt::append_string(const std::string &str) {
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FmtPart part = {};
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part.type = FmtPart::STRING;
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part.str = str;
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parts.push_back(part);
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}
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void Fmt::parse_rtlil(RTLIL::Cell *cell) {
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std::string fmt = cell->getParam(ID(FORMAT)).decode_string();
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RTLIL::SigSpec args = cell->getPort(ID(ARGS));
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parts.clear();
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FmtPart part;
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for (size_t i = 0; i < fmt.size(); i++) {
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if (fmt.substr(i, 2) == "}}")
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part.str += '}';
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else if (fmt.substr(i, 2) == "{{")
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part.str += '{';
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else if (fmt[i] == '}')
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log_assert(false && "Unexpected '}' in format string");
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else if (fmt[i] == '{') {
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if (!part.str.empty()) {
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part.type = FmtPart::STRING;
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parts.push_back(part);
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part = {};
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}
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size_t arg_size = 0;
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for (++i; i < fmt.size(); i++) {
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if (fmt[i] >= '0' && fmt[i] <= '9') {
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arg_size *= 10;
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arg_size += fmt[i] - '0';
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} else if (fmt[i] == ':') {
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break;
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} else {
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log_assert(false && "Unexpected character in format substitution");
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}
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}
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if (++i == fmt.size())
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log_assert(false && "Unexpected end in format substitution");
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if ((size_t)args.size() < arg_size)
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log_assert(false && "Format part overruns arguments");
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part.sig = args.extract(0, arg_size);
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args.remove(0, arg_size);
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if (fmt[i] == '>')
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part.justify = FmtPart::RIGHT;
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else if (fmt[i] == '<')
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part.justify = FmtPart::LEFT;
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else
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log_assert(false && "Unexpected justification in format substitution");
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if (++i == fmt.size())
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log_assert(false && "Unexpected end in format substitution");
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if (fmt[i] == '0' || fmt[i] == ' ')
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part.padding = fmt[i];
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else
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log_assert(false && "Unexpected padding in format substitution");
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if (++i == fmt.size())
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log_assert(false && "Unexpected end in format substitution");
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for (; i < fmt.size(); i++) {
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if (fmt[i] >= '0' && fmt[i] <= '9') {
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part.width *= 10;
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part.width += fmt[i] - '0';
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continue;
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} else if (fmt[i] == 'b') {
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part.type = FmtPart::INTEGER;
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part.base = 2;
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} else if (fmt[i] == 'o') {
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part.type = FmtPart::INTEGER;
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part.base = 8;
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} else if (fmt[i] == 'd') {
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part.type = FmtPart::INTEGER;
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part.base = 10;
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} else if (fmt[i] == 'h') {
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part.type = FmtPart::INTEGER;
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part.base = 16;
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} else if (fmt[i] == 'c') {
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part.type = FmtPart::CHARACTER;
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} else {
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log_assert(false && "Unexpected character in format substitution");
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}
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break;
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}
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if (++i == fmt.size())
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log_assert(false && "Unexpected end in format substitution");
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if (part.type == FmtPart::INTEGER) {
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if (fmt[i] == '+') {
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part.plus = true;
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if (++i == fmt.size())
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log_assert(false && "Unexpected end in format substitution");
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}
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if (fmt[i] == '0') {
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part.lzero = true;
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if (++i == fmt.size())
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log_assert(false && "Unexpected end in format substitution");
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}
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if (fmt[i] == 'u')
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part.signed_ = false;
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else if (fmt[i] == 's')
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part.signed_ = true;
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else
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log_assert(false && "Unexpected character in format substitution");
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if (++i == fmt.size())
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log_assert(false && "Unexpected end in format substitution");
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}
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if (fmt[i] != '}')
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log_assert(false && "Expected '}' after format substitution");
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parts.push_back(part);
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part = {};
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} else {
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part.str += fmt[i];
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}
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}
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if (!part.str.empty()) {
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part.type = FmtPart::STRING;
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parts.push_back(part);
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}
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}
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void Fmt::emit_rtlil(RTLIL::Cell *cell) const {
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std::string fmt;
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RTLIL::SigSpec args;
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for (auto &part : parts) {
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switch (part.type) {
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case FmtPart::STRING:
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for (char c : part.str) {
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if (c == '{')
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fmt += "{{";
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else if (c == '}')
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fmt += "}}";
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else
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fmt += c;
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}
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break;
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case FmtPart::CHARACTER:
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log_assert(part.sig.size() % 8 == 0);
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YS_FALLTHROUGH
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case FmtPart::INTEGER:
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args.append(part.sig);
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fmt += '{';
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fmt += std::to_string(part.sig.size());
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fmt += ':';
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if (part.justify == FmtPart::RIGHT)
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fmt += '>';
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else if (part.justify == FmtPart::LEFT)
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fmt += '<';
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else log_abort();
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log_assert(part.padding == '0' || part.padding == ' ');
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fmt += part.padding;
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fmt += std::to_string(part.width);
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if (part.type == FmtPart::INTEGER) {
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switch (part.base) {
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case 2: fmt += 'b'; break;
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case 8: fmt += 'o'; break;
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case 10: fmt += 'd'; break;
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case 16: fmt += 'h'; break;
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default: log_abort();
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}
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if (part.plus)
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fmt += '+';
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if (part.lzero)
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fmt += '0';
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fmt += part.signed_ ? 's' : 'u';
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} else if (part.type == FmtPart::CHARACTER) {
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fmt += 'c';
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} else log_abort();
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fmt += '}';
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break;
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default: log_abort();
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}
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}
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cell->setParam(ID(FORMAT), fmt);
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cell->setParam(ID(ARGS_WIDTH), args.size());
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cell->setPort(ID(ARGS), args);
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}
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static size_t compute_requried_decimal_places(size_t size, bool signed_)
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{
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BigUnsigned max;
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if (!signed_)
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max.setBit(size, true);
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else
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max.setBit(size - 1, true);
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size_t places = 0;
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while (!max.isZero()) {
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places++;
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max /= 10;
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}
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if (signed_)
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places++;
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return places;
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}
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static void apply_verilog_automatic_sizing(FmtPart &part)
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{
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if (part.base == 10) {
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size_t places = compute_requried_decimal_places(part.sig.size(), part.signed_);
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part.padding = ' ';
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part.width = std::max(part.width, places);
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} else {
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part.lzero = true;
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}
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}
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void Fmt::parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_like, int default_base, RTLIL::IdString task_name, RTLIL::IdString module_name)
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{
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parts.clear();
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auto arg = args.begin();
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for (; arg != args.end(); ++arg) {
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switch (arg->type) {
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case VerilogFmtArg::INTEGER: {
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FmtPart part = {};
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part.type = FmtPart::INTEGER;
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part.sig = arg->sig;
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part.base = default_base;
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part.signed_ = arg->signed_;
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apply_verilog_automatic_sizing(part);
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parts.push_back(part);
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break;
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}
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case VerilogFmtArg::STRING: {
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if (arg == args.begin() || !sformat_like) {
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const auto fmtarg = arg;
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const std::string &fmt = fmtarg->str;
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FmtPart part = {};
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for (size_t i = 0; i < fmt.size(); i++) {
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if (fmt[i] != '%') {
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part.str += fmt[i];
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} else if (fmt.substr(i, 2) == "%%") {
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i++;
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part.str += '%';
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} else if (fmt.substr(i, 2) == "%l" || fmt.substr(i, 2) == "%L") {
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i++;
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part.str += module_name.str();
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} else {
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if (!part.str.empty()) {
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part.type = FmtPart::STRING;
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parts.push_back(part);
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part = {};
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}
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if (++i == fmt.size()) {
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log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with incomplete format specifier in argument %zu.\n", task_name.c_str(), fmtarg - args.begin() + 1);
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}
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if (++arg == args.end()) {
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log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with fewer arguments than the format specifiers in argument %zu require.\n", task_name.c_str(), fmtarg - args.begin() + 1);
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}
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part.sig = arg->sig;
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part.signed_ = arg->signed_;
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for (; i < fmt.size(); i++) {
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if (fmt[i] == '-') {
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// left justify; not in IEEE 1800-2017 or verilator but iverilog has it
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part.justify = FmtPart::LEFT;
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} else if (fmt[i] == '+') {
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// always show sign; not in IEEE 1800-2017 or verilator but iverilog has it
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part.plus = true;
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} else break;
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}
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if (i == fmt.size()) {
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log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with incomplete format specifier in argument %zu.\n", task_name.c_str(), fmtarg - args.begin() + 1);
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}
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bool has_leading_zero = false, has_width = false;
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for (; i < fmt.size(); i++) {
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if (fmt[i] >= '0' && fmt[i] <= '9') {
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if (fmt[i] == '0' && !has_width) {
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has_leading_zero = true;
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} else {
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has_width = true;
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part.width *= 10;
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part.width += fmt[i] - '0';
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}
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continue;
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} else if (fmt[i] == 'b' || fmt[i] == 'B') {
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part.type = FmtPart::INTEGER;
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part.base = 2;
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} else if (fmt[i] == 'o' || fmt[i] == 'O') {
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part.type = FmtPart::INTEGER;
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part.base = 8;
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} else if (fmt[i] == 'd' || fmt[i] == 'D') {
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part.type = FmtPart::INTEGER;
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part.base = 10;
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} else if (fmt[i] == 'h' || fmt[i] == 'H' ||
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fmt[i] == 'x' || fmt[i] == 'X') {
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// hex digits always printed in lowercase for %h%x as well as %H%X
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part.type = FmtPart::INTEGER;
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part.base = 16;
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} else if (fmt[i] == 'c' || fmt[i] == 'C') {
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part.type = FmtPart::CHARACTER;
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part.sig.extend_u0(8);
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// %10c and %010c not fully defined in IEEE 1800-2017 and do different things in iverilog
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} else if (fmt[i] == 's' || fmt[i] == 'S') {
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part.type = FmtPart::CHARACTER;
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if ((part.sig.size() % 8) != 0)
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part.sig.extend_u0((part.sig.size() + 7) / 8 * 8);
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// %10s and %010s not fully defined in IEEE 1800-2017 and do the same thing in iverilog
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part.padding = ' ';
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} else {
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log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with unrecognized format character `%c' in argument %zu.\n", task_name.c_str(), fmt[i], fmtarg - args.begin() + 1);
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}
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break;
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}
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if (i == fmt.size()) {
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log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with incomplete format specifier in argument %zu.\n", task_name.c_str(), fmtarg - args.begin() + 1);
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}
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if (part.padding == '\0')
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part.padding = (has_leading_zero && part.justify == FmtPart::RIGHT) ? '0' : ' ';
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if (part.type == FmtPart::INTEGER) {
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if (part.base != 10 && part.plus) {
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log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with invalid format specifier in argument %zu.\n", task_name.c_str(), fmtarg - args.begin() + 1);
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}
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if (!has_leading_zero)
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apply_verilog_automatic_sizing(part);
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}
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parts.push_back(part);
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part = {};
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}
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}
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if (!part.str.empty()) {
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part.type = FmtPart::STRING;
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parts.push_back(part);
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}
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} else {
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FmtPart part = {};
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part.type = FmtPart::STRING;
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part.str = arg->str;
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parts.push_back(part);
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}
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break;
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}
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default: log_abort();
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}
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}
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}
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std::vector<VerilogFmtArg> Fmt::emit_verilog() const
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{
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std::vector<VerilogFmtArg> args;
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VerilogFmtArg fmt = {};
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fmt.type = VerilogFmtArg::STRING;
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for (auto &part : parts) {
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switch (part.type) {
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case FmtPart::STRING:
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for (char c : part.str) {
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if (c == '%')
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fmt.str += "%%";
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else
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fmt.str += c;
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}
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break;
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case FmtPart::INTEGER: {
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VerilogFmtArg arg = {};
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arg.type = VerilogFmtArg::INTEGER;
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arg.sig = part.sig;
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arg.signed_ = part.signed_;
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args.push_back(arg);
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fmt.str += '%';
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if (part.plus)
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fmt.str += '+';
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if (part.justify == FmtPart::LEFT)
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fmt.str += '-';
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if (part.width == 0) {
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if (!part.lzero)
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fmt.str += '0';
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} else if (part.width > 0) {
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log_assert(part.padding == ' ' || part.padding == '0');
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if (!part.lzero && part.base != 10)
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fmt.str += '0';
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else if (part.padding == '0')
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fmt.str += '0';
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fmt.str += std::to_string(part.width);
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}
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switch (part.base) {
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case 2: fmt.str += 'b'; break;
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case 8: fmt.str += 'o'; break;
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case 10: fmt.str += 'd'; break;
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case 16: fmt.str += 'h'; break;
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default: log_abort();
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}
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break;
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}
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case FmtPart::CHARACTER: {
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VerilogFmtArg arg;
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arg.type = VerilogFmtArg::INTEGER;
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arg.sig = part.sig;
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args.push_back(arg);
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fmt.str += '%';
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if (part.justify == FmtPart::LEFT)
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fmt.str += '-';
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if (part.sig.size() == 8) {
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if (part.width > 0) {
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log_assert(part.padding == '0' || part.padding == ' ');
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if (part.padding == '0')
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fmt.str += part.padding;
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fmt.str += std::to_string(part.width);
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}
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fmt.str += 'c';
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} else {
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log_assert(part.sig.size() % 8 == 0);
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if (part.width > 0) {
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log_assert(part.padding == ' '); // no zero padding
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fmt.str += std::to_string(part.width);
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}
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fmt.str += 's';
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}
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break;
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}
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}
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}
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args.insert(args.begin(), fmt);
|
||||
return args;
|
||||
}
|
||||
|
||||
std::string Fmt::render() const
|
||||
{
|
||||
std::string str;
|
||||
|
||||
for (auto &part : parts) {
|
||||
switch (part.type) {
|
||||
case FmtPart::STRING:
|
||||
str += part.str;
|
||||
break;
|
||||
|
||||
case FmtPart::INTEGER:
|
||||
case FmtPart::CHARACTER: {
|
||||
std::string buf;
|
||||
if (part.type == FmtPart::INTEGER) {
|
||||
RTLIL::Const value = part.sig.as_const();
|
||||
|
||||
if (!part.lzero && part.base != 10) {
|
||||
size_t minimum_size = 0;
|
||||
for (size_t index = 0; index < (size_t)value.size(); index++)
|
||||
if (value[index] != State::S0)
|
||||
minimum_size = index + 1;
|
||||
value = value.extract(0, minimum_size);
|
||||
}
|
||||
|
||||
if (part.base == 2) {
|
||||
buf = value.as_string();
|
||||
} else if (part.base == 8 || part.base == 16) {
|
||||
size_t step = (part.base == 16) ? 4 : 3;
|
||||
for (size_t index = 0; index < (size_t)value.size(); index += step) {
|
||||
RTLIL::Const subvalue = value.extract(index, min(step, value.size() - index));
|
||||
bool has_x = false, all_x = true, has_z = false, all_z = true;
|
||||
for (State bit : subvalue) {
|
||||
if (bit == State::Sx)
|
||||
has_x = true;
|
||||
else
|
||||
all_x = false;
|
||||
if (bit == State::Sz)
|
||||
has_z = true;
|
||||
else
|
||||
all_z = false;
|
||||
}
|
||||
if (all_x)
|
||||
buf += 'x';
|
||||
else if (all_z)
|
||||
buf += 'z';
|
||||
else if (has_x)
|
||||
buf += 'X';
|
||||
else if (has_z)
|
||||
buf += 'Z';
|
||||
else
|
||||
buf += "0123456789abcdef"[subvalue.as_int()];
|
||||
}
|
||||
std::reverse(buf.begin(), buf.end());
|
||||
} else if (part.base == 10) {
|
||||
bool has_x = false, all_x = true, has_z = false, all_z = true;
|
||||
for (State bit : value) {
|
||||
if (bit == State::Sx)
|
||||
has_x = true;
|
||||
else
|
||||
all_x = false;
|
||||
if (bit == State::Sz)
|
||||
has_z = true;
|
||||
else
|
||||
all_z = false;
|
||||
}
|
||||
if (all_x)
|
||||
buf += 'x';
|
||||
else if (all_z)
|
||||
buf += 'z';
|
||||
else if (has_x)
|
||||
buf += 'X';
|
||||
else if (has_z)
|
||||
buf += 'Z';
|
||||
else {
|
||||
bool negative = part.signed_ && value[value.size() - 1];
|
||||
RTLIL::Const absvalue;
|
||||
if (negative)
|
||||
absvalue = RTLIL::const_neg(value, {}, part.signed_, {}, value.size() + 1);
|
||||
else
|
||||
absvalue = value;
|
||||
log_assert(absvalue.is_fully_def());
|
||||
if (absvalue.is_fully_zero())
|
||||
buf += '0';
|
||||
while (!absvalue.is_fully_zero()) {
|
||||
buf += '0' + RTLIL::const_mod(absvalue, 10, part.signed_, false, 4).as_int();
|
||||
absvalue = RTLIL::const_div(absvalue, 10, part.signed_, false, absvalue.size());
|
||||
}
|
||||
if (negative || part.plus)
|
||||
buf += negative ? '-' : '+';
|
||||
std::reverse(buf.begin(), buf.end());
|
||||
}
|
||||
} else log_abort();
|
||||
} else if (part.type == FmtPart::CHARACTER) {
|
||||
buf = part.sig.as_const().decode_string();
|
||||
}
|
||||
|
||||
log_assert(part.width == 0 || part.padding != '\0');
|
||||
if (part.justify == FmtPart::RIGHT && buf.size() < part.width) {
|
||||
size_t pad_width = part.width - buf.size();
|
||||
if (part.padding == '0' && (buf.front() == '+' || buf.front() == '-')) {
|
||||
str += buf.front();
|
||||
buf.erase(0, 1);
|
||||
}
|
||||
str += std::string(pad_width, part.padding);
|
||||
}
|
||||
str += buf;
|
||||
if (part.justify == FmtPart::LEFT && buf.size() < part.width)
|
||||
str += std::string(part.width - buf.size(), part.padding);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return str;
|
||||
}
|
||||
90
kernel/fmt.h
Normal file
90
kernel/fmt.h
Normal file
|
|
@ -0,0 +1,90 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2020 whitequark <whitequark@whitequark.org>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef FMT_H
|
||||
#define FMT_H
|
||||
|
||||
#include "kernel/yosys.h"
|
||||
|
||||
YOSYS_NAMESPACE_BEGIN
|
||||
|
||||
// Verilog format argument, such as the arguments in:
|
||||
// $display("foo %d bar %01x", 4'b0, $signed(2'b11))
|
||||
struct VerilogFmtArg {
|
||||
enum {
|
||||
STRING = 0,
|
||||
INTEGER = 1,
|
||||
} type;
|
||||
|
||||
// All types
|
||||
std::string filename;
|
||||
unsigned first_line;
|
||||
|
||||
// STRING type
|
||||
std::string str;
|
||||
|
||||
// INTEGER type
|
||||
RTLIL::SigSpec sig;
|
||||
bool signed_ = false;
|
||||
};
|
||||
|
||||
// RTLIL format part, such as the substitutions in:
|
||||
// "foo {4: 4du} bar {2:01xs}"
|
||||
struct FmtPart {
|
||||
enum {
|
||||
STRING = 0,
|
||||
INTEGER = 1,
|
||||
CHARACTER = 2,
|
||||
} type;
|
||||
|
||||
// STRING type
|
||||
std::string str;
|
||||
|
||||
// INTEGER/CHARACTER type
|
||||
RTLIL::SigSpec sig;
|
||||
enum {
|
||||
RIGHT = 0,
|
||||
LEFT = 1,
|
||||
} justify = RIGHT;
|
||||
char padding = '\0';
|
||||
size_t width = 0;
|
||||
// INTEGER type
|
||||
unsigned base = 10;
|
||||
bool signed_ = false;
|
||||
bool lzero = false;
|
||||
bool plus = false;
|
||||
};
|
||||
|
||||
struct Fmt {
|
||||
std::vector<FmtPart> parts;
|
||||
|
||||
void append_string(const std::string &str);
|
||||
|
||||
void parse_rtlil(RTLIL::Cell *cell);
|
||||
void emit_rtlil(RTLIL::Cell *cell) const;
|
||||
|
||||
void parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_like, int default_base, RTLIL::IdString task_name, RTLIL::IdString module_name);
|
||||
std::vector<VerilogFmtArg> emit_verilog() const;
|
||||
|
||||
std::string render() const;
|
||||
};
|
||||
|
||||
YOSYS_NAMESPACE_END
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue