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fmt: remove lzero by lowering during Verilog parse
See https://github.com/YosysHQ/yosys/pull/3721#issuecomment-1502037466 -- this reduces logic within the cell, and makes the rules that apply much more clear.
This commit is contained in:
Charlotte
Marcelina Kościelnicka
parent
eb0fb4d662
commit
7f7c61c9f0
4 changed files with 82 additions and 41 deletions
100
kernel/fmt.cc
100
kernel/fmt.cc
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@ -130,12 +130,6 @@ void Fmt::parse_rtlil(const RTLIL::Cell *cell) {
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log_assert(false && "Unexpected end in format substitution");
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}
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if (fmt[i] == '0') {
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part.lzero = true;
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if (++i == fmt.size())
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log_assert(false && "Unexpected end in format substitution");
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}
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if (fmt[i] == 'u')
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part.signed_ = false;
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else if (fmt[i] == 's')
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@ -208,8 +202,6 @@ void Fmt::emit_rtlil(RTLIL::Cell *cell) const {
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}
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if (part.plus)
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fmt += '+';
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if (part.lzero)
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fmt += '0';
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fmt += part.signed_ ? 's' : 'u';
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} else if (part.type == FmtPart::CHARACTER) {
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fmt += 'c';
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@ -248,14 +240,72 @@ static size_t compute_required_decimal_places(size_t size, bool signed_)
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return places;
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}
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static void apply_verilog_automatic_sizing(FmtPart &part)
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static size_t compute_required_nondecimal_places(size_t size, unsigned base)
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{
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log_assert(base != 10);
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BigUnsigned max;
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max.setBit(size - 1, true);
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size_t places = 0;
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while (!max.isZero()) {
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places++;
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max /= base;
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}
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return places;
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}
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// Only called for integers, either when:
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//
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// (a) passed without a format string (e.g. "$display(a);"), or
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//
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// (b) the corresponding format specifier has no leading zero, e.g. "%b",
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// "%20h", "%-10d".
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//
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// In these cases, for binary/octal/hex, we always zero-pad to the size of the
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// signal; i.e. whether "%h" or "%10h" or "%-20h" is used, if the corresponding
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// signal is 32'h1234, "00001234" will always be a substring of the output.
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//
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// For case (a), we have no specified width, so there is nothing more to do.
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//
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// For case (b), because we are only called with no leading zero on the
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// specifier, any specified width beyond the signal size is therefore space
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// padding, whatever the justification.
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//
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// For decimal, we do no zero-padding, instead space-padding to the size
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// required for the signal's largest value. This is per other Verilog
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// implementations, and intuitively makes sense as decimal representations lack
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// a discrete mapping of digits to bit groups. Decimals may also show sign and
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// must accommodate this, whereas other representations do not.
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void Fmt::apply_verilog_automatic_sizing_and_add(FmtPart &part)
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{
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if (part.base == 10) {
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size_t places = compute_required_decimal_places(part.sig.size(), part.signed_);
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part.padding = ' ';
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part.width = std::max(part.width, places);
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} else {
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part.lzero = true;
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parts.push_back(part);
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return;
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}
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part.padding = '0';
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size_t places = compute_required_nondecimal_places(part.sig.size(), part.base);
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if (part.width < places) {
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part.justify = FmtPart::RIGHT;
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part.width = places;
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parts.push_back(part);
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} else if (part.width == places) {
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parts.push_back(part);
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} else if (part.width > places) {
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auto gap = std::string(part.width - places, ' ');
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part.width = places;
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if (part.justify == FmtPart::RIGHT) {
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append_string(gap);
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parts.push_back(part);
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} else {
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part.justify = FmtPart::RIGHT;
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parts.push_back(part);
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append_string(gap);
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}
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}
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}
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@ -272,8 +322,7 @@ void Fmt::parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_lik
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part.sig = arg->sig;
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part.base = default_base;
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part.signed_ = arg->signed_;
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apply_verilog_automatic_sizing(part);
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parts.push_back(part);
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apply_verilog_automatic_sizing_and_add(part);
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break;
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}
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@ -379,15 +428,13 @@ void Fmt::parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_lik
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if (part.padding == '\0')
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part.padding = (has_leading_zero && part.justify == FmtPart::RIGHT) ? '0' : ' ';
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if (part.type == FmtPart::INTEGER) {
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if (part.base != 10 && part.plus) {
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log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with invalid format specifier in argument %zu.\n", task_name.c_str(), fmtarg - args.begin() + 1);
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}
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if (!has_leading_zero)
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apply_verilog_automatic_sizing(part);
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}
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if (part.type == FmtPart::INTEGER && part.base != 10 && part.plus)
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log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with invalid format specifier in argument %zu.\n", task_name.c_str(), fmtarg - args.begin() + 1);
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parts.push_back(part);
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if (part.type == FmtPart::INTEGER && !has_leading_zero)
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apply_verilog_automatic_sizing_and_add(part);
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else
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parts.push_back(part);
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part = {};
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}
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}
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@ -439,13 +486,10 @@ std::vector<VerilogFmtArg> Fmt::emit_verilog() const
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if (part.justify == FmtPart::LEFT)
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fmt.str += '-';
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if (part.width == 0) {
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if (!part.lzero)
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fmt.str += '0';
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fmt.str += '0';
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} else if (part.width > 0) {
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log_assert(part.padding == ' ' || part.padding == '0');
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if (!part.lzero && part.base != 10)
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fmt.str += '0';
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else if (part.padding == '0')
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if (part.base != 10 || part.padding == '0')
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fmt.str += '0';
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fmt.str += std::to_string(part.width);
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}
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@ -567,7 +611,6 @@ void Fmt::emit_cxxrtl(std::ostream &f, std::function<void(const RTLIL::SigSpec &
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f << ", " << part.width;
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f << ", " << part.base;
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f << ", " << part.signed_;
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f << ", " << part.lzero;
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f << ", " << part.plus;
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f << ')';
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break;
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@ -584,7 +627,6 @@ void Fmt::emit_cxxrtl(std::ostream &f, std::function<void(const RTLIL::SigSpec &
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f << ", " << part.width;
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f << ", " << part.base;
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f << ", " << part.signed_;
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f << ", " << part.lzero;
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f << ", " << part.plus;
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f << ')';
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break;
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@ -612,7 +654,7 @@ std::string Fmt::render() const
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if (part.type == FmtPart::INTEGER) {
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RTLIL::Const value = part.sig.as_const();
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if (!part.lzero && part.base != 10) {
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if (part.base != 10) {
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size_t minimum_size = 0;
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for (size_t index = 0; index < (size_t)value.size(); index++)
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if (value[index] != State::S0)
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@ -75,7 +75,6 @@ struct FmtPart {
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// INTEGER type
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unsigned base = 10;
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bool signed_ = false;
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bool lzero = false;
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bool plus = false;
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// TIME type
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@ -83,6 +82,7 @@ struct FmtPart {
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};
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struct Fmt {
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public:
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std::vector<FmtPart> parts;
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void append_string(const std::string &str);
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@ -96,6 +96,9 @@ struct Fmt {
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void emit_cxxrtl(std::ostream &f, std::function<void(const RTLIL::SigSpec &)> emit_sig) const;
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std::string render() const;
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private:
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void apply_verilog_automatic_sizing_and_add(FmtPart &part);
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};
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YOSYS_NAMESPACE_END
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