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Code Activity
13739 commits 93 branches 53 tags 44 MiB
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2291 commits

Author SHA1 Message Date
Marcin Kościelnicki
a235250403 xilinx: Add xilinx_dffopt pass (#1557) 2019-12-18 13:43:43 +01:00
Marcin Kościelnicki
aff6ad1ce0 xilinx: Improve flip-flop handling. 
This adds support for infering more kinds of flip-flops:

- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable

Some passes have been moved (and some added) in order for dff2dffs to
work correctly.

This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities).  Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
 2019-12-18 13:43:43 +01:00
Eddie Hung
a73f96594f
Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram 
xilinx: add LUTRAM rules for RAM32M, RAM64M
 2019-12-16 21:48:21 -08:00
Eddie Hung
5a00d5578c Add unconditional match blocks for force RAM 2019-12-16 13:31:15 -08:00
Eddie Hung
d910bec8e0 Update xc7/xcu bram rules 2019-12-16 13:00:58 -08:00
Eddie Hung
5d00996426 Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xilinx_lutram 2019-12-16 12:06:47 -08:00
Eddie Hung
7545ab3814 Populate DID/DOD even if unused 2019-12-16 11:57:04 -08:00
Eddie Hung
c4d37813cb Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q 2019-12-16 10:41:13 -08:00
Diego H
f3f59910eb Removing fixed attribute value to !ramstyle rules 2019-12-15 23:51:58 -06:00
Diego H
b35559fc33 Merging attribute rules into a single match block; Adding tests 2019-12-15 23:33:09 -06:00
Diego H
266993408a Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific 2019-12-13 15:43:24 -06:00
Eddie Hung
52875b0d61
Merge pull request #1533 from dh73/bram_xilinx 
Adjust Xilinx xc7/xcu BRAM min bits threshold for RAMB18E1
 2019-12-13 12:01:03 -08:00
Eddie Hung
c3262d6075 Disable RAM16X1D match rule; carry-over from LUT4 arches 2019-12-13 08:59:17 -08:00
Eddie Hung
d6514fc2e1 RAM64M8 to also have [5:0] for address 2019-12-13 08:54:19 -08:00
Eddie Hung
dd7d2d8db6 Duplicate tribuf call, credit to @mwkmwkmwk 2019-12-13 08:51:05 -08:00
Eddie Hung
8925bf4b96 Add RAM32X6SDP and RAM64X3SDP modes 2019-12-12 18:52:28 -08:00
Eddie Hung
50e0c83560 Fix RAM64M model to have 6 bit address bus 2019-12-12 18:52:03 -08:00
Eddie Hung
7a9d1be97d Add memory rules for RAM16X1D, RAM32M, RAM64M 2019-12-12 17:44:59 -08:00
Diego H
751a18d7e9 Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test. 2019-12-12 17:32:58 -06:00
Eddie Hung
bea15b537b Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-12 14:57:17 -08:00
Eddie Hung
9ab1feeaf1 abc9_map.v: fix Xilinx LUTRAM 2019-12-12 14:56:52 -08:00
Eddie Hung
3eed8835b5 abc9_map.v: fix Xilinx LUTRAM 2019-12-12 14:56:15 -08:00
Eddie Hung
3bd623bb05 synth_xilinx: error out if tristate without '-iopad' 2019-12-12 14:33:33 -08:00
Diego H
937ec1ee78 Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1 2019-12-12 13:50:36 -06:00
Diego H
ab6ac8327f Merge https://github.com/YosysHQ/yosys into bram_xilinx 2019-12-12 13:40:05 -06:00
Eddie Hung
f022645cd2 Fix bitwidth mismatch; suppresses iverilog warning 2019-12-11 13:02:07 -08:00
David Shah
613334d9dc
Merge pull request #1564 from ZirconiumX/intel_housekeeping 
Intel housekeeping
 2019-12-11 08:46:10 +00:00
Dan Ravensloft
85a14895ca synth_intel: a10gx -> arria10gx 2019-12-10 13:48:10 +00:00
Dan Ravensloft
eab3272cde synth_intel: cyclone10 -> cyclone10lp 2019-12-10 13:47:58 +00:00
Eddie Hung
7e5602ad17
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr 
Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
 2019-12-09 17:38:48 -08:00
Eddie Hung
49c2e59b2a Fix comment 2019-12-09 15:44:19 -08:00
Eddie Hung
fb203d2a2c ice40_opt to restore attributes/name when unwrapping 2019-12-09 14:29:29 -08:00
Eddie Hung
500ed9b501 Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4 2019-12-09 12:45:22 -08:00
Eddie Hung
e05372778a ice40_wrapcarry to really preserve attributes via -unwrap option 2019-12-09 11:48:28 -08:00
David Shah
184c0e796a ecp5: Add support for mapping PRLD FFs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-07 13:04:36 +00:00
Eddie Hung
a46a7e8a67 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-06 23:22:52 -08:00
Eddie Hung
98c9ea605b techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger 2019-12-06 17:05:02 -08:00
Eddie Hung
c767525441 Remove creation of $abc9_control_wire 2019-12-06 16:23:09 -08:00
Eddie Hung
ec0acc9f85 abc9 to use mergeability class to differentiate sync/async 2019-12-06 00:12:37 -08:00
Eddie Hung
02786b0aa0 Remove clkpart 2019-12-05 17:25:26 -08:00
Eddie Hung
864bff14f1 Revert "Special abc9_clock wire to contain only clock signal" 
This reverts commit 6a2eb5d8f9.
 2019-12-05 11:11:53 -08:00
Eddie Hung
0d248dd7ba Missing wire declaration 2019-12-04 23:04:40 -08:00
Eddie Hung
19bc429482 abc9_map.v to transform INIT=1 to INIT=0 2019-12-04 21:36:41 -08:00
Eddie Hung
258a34e6f1 Oh deary me 2019-12-04 20:33:24 -08:00
Eddie Hung
b43986c5a1 output reg Q -> output Q to suppress warning 2019-12-04 16:34:34 -08:00
Eddie Hung
31ef4cc704 abc9_map.v to do `zinit' and make INIT = 1'b0 2019-12-04 16:11:02 -08:00
Marcin Kościelnicki
fcce94010f
xilinx: Add tristate buffer mapping. (#1528) 
Fixes #1225.
 2019-12-04 09:44:00 +01:00
Marcin Kościelnicki
10014e2643
xilinx: Add models for LUTRAM cells. (#1537) 2019-12-04 06:31:09 +01:00
Eddie Hung
a181ff66d3 Add abc9_init wire, attach to abc9_flop cell 2019-12-03 18:47:09 -08:00
Eddie Hung
f98aa1c13f Revert "Add INIT value to abc9_control" 
This reverts commit 19bfb41958.
 2019-12-03 15:40:44 -08:00