mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-22 16:45:32 +00:00
Code Activity
13564 commits 93 branches 53 tags 44 MiB
Commit graph

2266 commits

Author SHA1 Message Date
Eddie Hung
544843da71 techmap inside map_cells stage 2019-04-05 12:55:52 -07:00
Eddie Hung
7b7ddbdba7 Merge branch 'map_cells_before_map_luts' into xc7srl 2019-04-04 08:13:34 -07:00
Eddie Hung
e3f20b17af Missing techmap entry in help 2019-04-04 08:13:10 -07:00
Eddie Hung
2fb02247a7 Use soft-logic, not LUT3 instantiation 2019-04-04 08:10:40 -07:00
Eddie Hung
572603409c Merge branch 'map_cells_before_map_luts' into xc7srl 2019-04-04 07:54:42 -07:00
Eddie Hung
d9cb787391 synth_xilinx to map_cells before map_luts 2019-04-04 07:48:13 -07:00
Eddie Hung
77755b5a66 Cleanup comments 2019-04-04 07:41:40 -07:00
Eddie Hung
736e19f02d t:$dff* -> t:$dff t:$dffe 2019-04-04 07:39:19 -07:00
Eddie Hung
0e2d929cea -nosrl meant when -nobram 2019-04-03 08:28:07 -07:00
Eddie Hung
ff385a5ad0 Remove duplicate STARTUPE2 2019-04-03 08:14:09 -07:00
Eddie Hung
88630cd02c Disable shregmap in synth_xilinx if -retime 2019-04-03 07:14:20 -07:00
Miodrag Milanovic
df92e9bdc2 Make nobram false by default for gowin 2019-04-02 19:21:01 +02:00
Eddie Hung
f9fb05cf66 synth_xilinx to use shregmap with -minlen 3 2019-03-25 13:18:55 -07:00
Eddie Hung
46753cf89f Merge remote-tracking branch 'origin/master' into xc7srl 2019-03-22 13:10:42 -07:00
David Shah
46f6a60d58 xilinx: Add keep attribute where appropriate 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 13:57:17 +00:00
Eddie Hung
4cc6b3e942 Add '-nosrl' option to synth_xilinx 2019-03-21 15:04:44 -07:00
Eddie Hung
81c207fb9b Fine tune cells_map.v 2019-03-20 10:55:14 -07:00
Eddie Hung
505e4c2d59 Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length 2019-03-19 21:58:05 -07:00
Eddie Hung
5445cd4d00 Add support for variable length Xilinx SRL > 128 2019-03-19 17:44:33 -07:00
Eddie Hung
ae2a625d05 Restore original synth_xilinx commands 2019-03-19 16:14:08 -07:00
Eddie Hung
9156e18f92 Fix spacing 2019-03-19 16:12:32 -07:00
Eddie Hung
f239cb821e Fix INIT for variable length SRs that have been bumped up one 2019-03-19 14:54:43 -07:00
Eddie Hung
24553326dd Merge remote-tracking branch 'origin/master' into xc7srl 2019-03-19 13:11:30 -07:00
Clifford Wolf
fe1fb1336b Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-19 20:30:28 +01:00
Eddie Hung
fadeadb8c8 Only accept <128 for variable length, only if $shiftx exclusive 2019-03-16 08:51:13 -07:00
Eddie Hung
29a8d4745e Cleanup synth_xilinx 2019-03-15 23:01:40 -07:00
Eddie Hung
06f8f2654a Working 2019-03-15 19:13:40 -07:00
Eddie Hung
e7ef7fa443 Reverse bits in INIT parameter for Xilinx, since MSB is shifted first 2019-03-14 09:38:42 -07:00
Eddie Hung
af5706c2a3 Misspell 2019-03-14 09:06:56 -07:00
Eddie Hung
8af9979aab Revert "Add shregmap -init_msb_first and use in synth_xilinx" 
This reverts commit 26ecbc1aee.
 2019-03-14 09:01:48 -07:00
Eddie Hung
f1a8e8a480 Merge remote-tracking branch 'origin/master' into xc7srl 2019-03-14 08:59:19 -07:00
Eddie Hung
26ecbc1aee Add shregmap -init_msb_first and use in synth_xilinx 2019-03-14 08:10:02 -07:00
Eddie Hung
79b4a275ce Fix cells_map for SRL 2019-03-14 08:09:48 -07:00
Eddie Hung
edca2f1163 Move shregmap until after first techmap 2019-03-13 17:13:52 -07:00
Eddie Hung
24f129ddfb Refactor $__SHREG__ in cells_map.v 2019-03-13 16:17:54 -07:00
Clifford Wolf
9284cf92b8 Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-12 20:14:18 +01:00
Clifford Wolf
ff4c2a14ae Fix typo in ice40_braminit help msg 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-09 13:24:55 -08:00
Clifford Wolf
2ace1b0041
Merge pull request #859 from smunaut/ice40_braminit 
iCE40 BRAM primitives init from file
 2019-03-09 13:24:10 -08:00
Sylvain Munaut
5b6f591033 ice40: Run ice40_braminit pass by default 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-03-08 00:15:46 +01:00
Sylvain Munaut
e71055cfe8 ice40: Add ice40_braminit pass to allow initialization of BRAM from file 
This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will
initialize content from a hex file. Same behavior is imlemented in the
simulation model and in a new pass for actual synthesis

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-03-08 00:15:46 +01:00
Clifford Wolf
350dfd3745 Add link to SF2 / igloo2 macro library guide 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-07 09:08:26 -08:00
Clifford Wolf
8b0719d1e3 Improvements in sf2 cells_sim.v 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-06 16:18:49 -08:00
Clifford Wolf
2d2c1617ee Add sf2 techmap rules for more FF types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-06 15:47:54 -08:00
Clifford Wolf
78762316aa Refactor SF2 iobuf insertion, Add clkint insertion 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-06 00:41:02 -08:00
Clifford Wolf
da5181a3df Improvements in SF2 flow and demo 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-05 20:36:00 -08:00
Clifford Wolf
bfcd46dbd3
Merge pull request #842 from litghost/merge_upstream 
Changes required for VPR place and route in synth_xilinx
 2019-03-05 15:33:19 -08:00
Clifford Wolf
724576a4e2
Merge pull request #850 from daveshah1/ecp5_warn_conflict 
ecp5: Demote conflicting FF init values to a warning
 2019-03-05 15:23:01 -08:00
Clifford Wolf
13844c7658 Use "write_edif -pvector bra" for Xilinx EDIF files 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-05 15:16:13 -08:00
Keith Rothman
228f132ec3 Revert BRAM WRITE_MODE changes. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-04 09:22:22 -08:00
David Shah
777864d02e ecp5: Demote conflicting FF init values to a warning 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-04 11:26:20 +00:00