876 commits

Author	SHA1	Message	Date
David Shah	c43b0c4b49	[wip] DSP48E1 sim model improvements ... Signed-off-by: David Shah <dave@ds0.me>	2019-08-06 18:47:18 +01:00
David Shah	7a563d0b92	[wip] DSP48E1 sim model improvements ... Signed-off-by: David Shah <dave@ds0.me>	2019-08-06 13:23:42 +01:00
Eddie Hung	fc0b5d5ab6	Change $__softmul back to $mul	2019-08-01 12:45:14 -07:00
Eddie Hung	ed303b07b7	Merge remote-tracking branch 'origin/master' into xc7dsp	2019-08-01 12:02:16 -07:00
Eddie Hung	66806085db	RST -> RSTBRST for RAMB8BWER	2019-07-29 16:05:44 -07:00
David Shah	ab607e896e	xilinx: Fix missing cell name underscore in cells_map.v ... Signed-off-by: David Shah <dave@ds0.me>	2019-07-25 08:19:07 +01:00
Eddie Hung	601fac97e4	Add params	2019-07-18 21:02:49 -07:00
Eddie Hung	43616e1414	Update Makefile too	2019-07-18 14:51:55 -07:00
Eddie Hung	b97fe6e866	Work in progress for renaming labels/options in synth_xilinx	2019-07-18 14:20:43 -07:00
Eddie Hung	5562cb08a4	Use single DSP_SIGNEDONLY macro	2019-07-18 13:09:55 -07:00
Eddie Hung	e3f8e59f18	Make all operands signed	2019-07-17 14:25:40 -07:00
Eddie Hung	58e63feae1	Update comment	2019-07-17 13:26:17 -07:00
Eddie Hung	c501aa5ee8	Signedness	2019-07-16 15:54:27 -07:00
Eddie Hung	6390c535ba	Revert drop down to 24x16 multipliers for all	2019-07-16 14:30:25 -07:00
Eddie Hung	569cd66764	Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp	2019-07-16 14:18:36 -07:00
Eddie Hung	5d1ce04381	Add support for {A,B,P}REG in DSP48E1	2019-07-16 14:05:50 -07:00
David Shah	d38df68d26	xilinx: Add correct signed behaviour to DSP48E1 model ... Signed-off-by: David Shah <dave@ds0.me>	2019-07-16 17:53:08 +01:00
David Shah	95c8d27b0b	xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 signed) ... Signed-off-by: David Shah <dave@ds0.me>	2019-07-16 16:47:53 +01:00
Eddie Hung	5f00d335d4	Oops forgot these files	2019-07-15 15:03:15 -07:00
Eddie Hung	0c7ee6d0fa	Move DSP mapping back out to dsp_map.v	2019-07-15 14:18:44 -07:00
Eddie Hung	20e3d2d9b0	Move DSP48E1 model out of cells_xtra, initial multiply one in cells_sim	2019-07-15 11:13:22 -07:00
Eddie Hung	146451a767	Merge remote-tracking branch 'origin/master' into xc7dsp	2019-07-15 09:49:41 -07:00
Eddie Hung	1c9f3fadb9	Add Tsu offset to boxes, and comments	2019-07-11 17:17:26 -07:00
Eddie Hung	d386177e6d	ABC doesn't like negative delays in flop boxes...	2019-07-11 17:09:17 -07:00
Eddie Hung	3ef927647c	Fix FDCE_1 box	2019-07-11 14:25:47 -07:00
Eddie Hung	1ada568134	Revert "$pastQ should be first input" ... This reverts commit 8f9d529929.	2019-07-11 14:23:45 -07:00
Eddie Hung	854333f2af	Propagate INIT attr	2019-07-11 13:55:47 -07:00
Eddie Hung	8f9d529929	$pastQ should be first input	2019-07-11 13:54:40 -07:00
Eddie Hung	021f8e5492	Fix typo	2019-07-11 13:23:07 -07:00
Eddie Hung	19c1c3cfa3	Merge pull request #1182 from koriakin/xc6s-bram ... synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 12:55:35 -07:00
Marcin Kościelnicki	a9efacd01d	xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.	2019-07-11 21:13:12 +02:00
Eddie Hung	8fef4c3594	Simplify to $__ABC_ASYNC box	2019-07-11 10:52:33 -07:00
Eddie Hung	93fbd56db1	$__ABC_FD_ASYNC_MUX.Q -> Y	2019-07-11 10:25:59 -07:00
Marcin Kościelnicki	ce250b341c	synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 14:45:48 +02:00
Eddie Hung	d357431df1	Restore from master	2019-07-10 22:54:39 -07:00
Eddie Hung	f984e0cb34	Another typo	2019-07-10 22:33:35 -07:00
Eddie Hung	ea6ffea2cd	Fix clk_pol for FD*_1	2019-07-10 20:10:20 -07:00
Eddie Hung	7899a06ed6	Another typo	2019-07-10 19:59:24 -07:00
Eddie Hung	ad35b509de	Another typo	2019-07-10 19:05:53 -07:00
Eddie Hung	f3511e4f93	Use \$currQ	2019-07-10 19:01:13 -07:00
Eddie Hung	f030be3f1c	Preserve all parameters, plus some extra ones for clk/en polarity	2019-07-10 18:57:11 -07:00
Eddie Hung	4a995c5d80	Change how to specify flops to ABC again	2019-07-10 17:54:56 -07:00
Eddie Hung	3bb48facb2	Remove params from FD*_1 variants	2019-07-10 17:17:54 -07:00
Eddie Hung	0372c900e8	Fix typo, and have !{PRE,CLR} behave as CE	2019-07-10 17:15:49 -07:00
Eddie Hung	7b2599cb94	Move ABC FF stuff to abc_ff.v; add support for other FD* types	2019-07-10 17:06:05 -07:00
Eddie Hung	0ab8f28bc7	Uncomment IS_C_INVERTED parameter	2019-07-10 16:23:15 -07:00
Eddie Hung	838ae1a14c	synth_xilinx's map_cells stage to techmap ff_map.v	2019-07-10 16:15:57 -07:00
Eddie Hung	73c8f1a59e	Fix box numbering	2019-07-10 16:12:33 -07:00
Eddie Hung	052060f109	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-07-10 16:05:41 -07:00
Eddie Hung	b33ecd2a74	Move dsp_map.v into cells_map.v; cleanup synth_xilinx a little	2019-07-10 16:00:03 -07:00