3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-08 10:25:19 +00:00

Another typo

This commit is contained in:
Eddie Hung 2019-07-10 19:05:53 -07:00
parent e603d719d6
commit ad35b509de

View file

@ -68,7 +68,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
);
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
generate
if (IS_PRE_INVERTED)
if (IS_CLR_INVERTED)
\$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
else
\$__ABC_FD_ASYNC_MUX abc_async_mux (.A(1'b0), .B(\$currQ ), .S(CLR), .Y(Q));