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tests
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Improved xilinx "bram1" test
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2015-04-09 17:12:12 +02:00 |
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.gitignore
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Added support for initialized xilinx brams
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2015-04-06 17:07:10 +02:00 |
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abc_ff.v
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Simplify to $__ABC_ASYNC box
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2019-07-11 10:52:33 -07:00 |
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abc_xc7.box
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$pastQ should be first input
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2019-07-11 13:54:40 -07:00 |
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abc_xc7.lut
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Simplify comment
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2019-06-17 19:14:41 -07:00 |
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abc_xc7_nowide.lut
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Add _nowide variants of LUT libraries in -nowidelut flows
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2019-06-26 10:23:29 -07:00 |
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arith_map.v
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Instead of MUXCY/XORCY use CARRY4 (with timing)
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2019-05-21 16:19:45 -07:00 |
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brams.txt
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Added read-enable to memory model
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2015-09-25 12:23:11 +02:00 |
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brams_bb.v
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Remove WIP ABC9 flop support
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2019-06-14 10:37:52 -07:00 |
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brams_init.py
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Squelch trailing whitespace, including meta-whitespace
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2018-03-11 16:03:41 +01:00 |
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brams_map.v
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Revert BRAM WRITE_MODE changes.
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2019-03-04 09:22:22 -08:00 |
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cells_map.v
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Add some spacing
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2019-07-10 12:32:33 -07:00 |
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cells_sim.v
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Revert "Fix broken MUXFx box, use MUXF7x2 box instead"
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2019-07-01 14:01:09 -07:00 |
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cells_xtra.sh
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Merge remote-tracking branch 'origin/master' into xaig
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2019-06-25 09:33:11 -07:00 |
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cells_xtra.v
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Merge remote-tracking branch 'origin/master' into xaig
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2019-06-25 09:33:11 -07:00 |
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drams.txt
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Add RAM32X1D support
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2019-06-24 16:16:50 -07:00 |
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drams_map.v
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Add RAM32X1D support
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2019-06-24 16:16:50 -07:00 |
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ff_map.v
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Restore from master
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2019-07-10 22:54:39 -07:00 |
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lut_map.v
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Really permute Xilinx LUT mappings as default LUT6.I5:A6
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2019-06-18 11:48:48 -07:00 |
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Makefile.inc
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Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-07-10 16:05:41 -07:00 |
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mux_map.v
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Change synth_xilinx's -nomux to -minmuxf <int>
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2019-06-24 10:04:01 -07:00 |
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synth_xilinx.cc
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Move ABC FF stuff to abc_ff.v; add support for other FD* types
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2019-07-10 17:06:05 -07:00 |
