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yosys/techlibs/xilinx
History
Marcin Kościelnicki ce250b341c synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
..
tests Improved xilinx "bram1" test 2015-04-09 17:12:12 +02:00
.gitignore Added support for initialized xilinx brams 2015-04-06 17:07:10 +02:00
abc_xc7.box Fix $__XILINX_MUXF78 box timing 2019-07-01 14:04:06 -07:00
abc_xc7.lut Simplify comment 2019-06-17 19:14:41 -07:00
abc_xc7_nowide.lut Add _nowide variants of LUT libraries in -nowidelut flows 2019-06-26 10:23:29 -07:00
arith_map.v Instead of MUXCY/XORCY use CARRY4 (with timing) 2019-05-21 16:19:45 -07:00
brams_init.py synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
cells_map.v Add some spacing 2019-07-10 12:32:33 -07:00
cells_sim.v Revert "Fix broken MUXFx box, use MUXF7x2 box instead" 2019-07-01 14:01:09 -07:00
cells_xtra.sh Merge remote-tracking branch 'origin/master' into xaig 2019-06-25 09:33:11 -07:00
cells_xtra.v Merge remote-tracking branch 'origin/master' into xaig 2019-06-25 09:33:11 -07:00
drams.txt Add RAM32X1D support 2019-06-24 16:16:50 -07:00
drams_map.v Add RAM32X1D support 2019-06-24 16:16:50 -07:00
ff_map.v Cleanup 2019-06-05 12:28:46 -07:00
lut_map.v Really permute Xilinx LUT mappings as default LUT6.I5:A6 2019-06-18 11:48:48 -07:00
Makefile.inc synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
mux_map.v Change synth_xilinx's -nomux to -minmuxf <int> 2019-06-24 10:04:01 -07:00
synth_xilinx.cc synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
xc6s_brams.txt synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
xc6s_brams_bb.v synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
xc6s_brams_map.v synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
xc7_brams.txt synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
xc7_brams_bb.v synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
xc7_brams_map.v synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00