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xilinx: Add correct signed behaviour to DSP48E1 model
Signed-off-by: David Shah <dave@ds0.me>
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@ -506,6 +506,6 @@ module DSP48E1 (
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if (PCIN != 48'b0) $fatal(1, "Unsupported PCIN value");
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if (CARRYIN != 1'b0) $fatal(1, "Unsupported CARRYIN value");
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`endif
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P[42:0] <= A[24:0] * B;
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P[42:0] <= $signed(A[24:0]) * $signed(B);
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end
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endmodule
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