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Code Activity

xilinx: Add correct signed behaviour to DSP48E1 model

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2019-07-16 17:53:08 +01:00
parent 95c8d27b0b
commit d38df68d26
1 changed files with 1 additions and 1 deletions
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2
techlibs/xilinx/cells_sim.v
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@ -506,6 +506,6 @@ module DSP48E1 (
if (PCIN != 48'b0) $fatal(1, "Unsupported PCIN value");
if (CARRYIN != 1'b0) $fatal(1, "Unsupported CARRYIN value");
`endif
P[42:0] <= A[24:0] * B;
P[42:0] <= $signed(A[24:0]) * $signed(B);
end
endmodule