fayalite

Author	SHA1	Message	Date
Jacob Lifshay	d1bd176b28	implement simulation of extern modules All checks were successful / deps (pull_request) Successful in 11m39s Details / test (pull_request) Successful in 3m55s Details	2025-03-21 01:47:14 -07:00
Jacob Lifshay	d4ea826051	sim: fix "label address not set" bug when the last Assignment is conditional All checks were successful / deps (pull_request) Successful in 23s Details / test (pull_request) Successful in 3m32s Details / deps (push) Successful in 15s Details / test (push) Successful in 3m58s Details	2025-01-15 19:04:40 -08:00
Jacob Lifshay	404a2ee043	tests/sim: add test_array_rw All checks were successful / deps (pull_request) Successful in 19s Details / test (pull_request) Successful in 3m34s Details / deps (push) Successful in 15s Details / test (push) Successful in 4m2s Details	2025-01-12 21:38:59 -08:00
Jacob Lifshay	e3a2ccd41c	properly handle duplicate names in vcd All checks were successful / deps (pull_request) Successful in 14s Details / test (pull_request) Successful in 3m43s Details / deps (push) Successful in 15s Details / test (push) Successful in 4m8s Details	2025-01-09 22:52:22 -08:00
Jacob Lifshay	36bad52978	sim: fix sim.write to struct All checks were successful / deps (pull_request) Successful in 15s Details / test (pull_request) Successful in 5m16s Details / deps (push) Successful in 14s Details / test (push) Successful in 5m14s Details	2024-12-18 20:50:50 -08:00
Jacob Lifshay	21c73051ec	sim: add SimValue and reading/writing more than just a scalar All checks were successful / deps (pull_request) Successful in 14s Details / test (pull_request) Successful in 5m14s Details / deps (push) Successful in 14s Details / test (push) Successful in 5m12s Details	2024-12-18 01:39:35 -08:00
Jacob Lifshay	2af38de900	add more memory tests Some checks failed / deps (push) Successful in 19s Details / test (push) Has been cancelled Details / deps (pull_request) Successful in 14s Details / test (pull_request) Successful in 5m21s Details	2024-12-13 15:04:48 -08:00
Jacob Lifshay	c756aeec70	tests/sim: add test for memory rw port All checks were successful / deps (push) Successful in 18s Details / test (push) Successful in 5m20s Details / deps (pull_request) Successful in 13s Details / test (pull_request) Successful in 6m32s Details	2024-12-12 20:50:41 -08:00
Jacob Lifshay	903ca1bf30	sim: simple memory test works! All checks were successful / deps (push) Successful in 17s Details / test (push) Successful in 5m20s Details / deps (pull_request) Successful in 14s Details / test (pull_request) Successful in 5m24s Details	2024-12-12 19:47:57 -08:00
Jacob Lifshay	393f78a14d	sim: add WIP memory test All checks were successful / deps (push) Successful in 18s Details / test (push) Successful in 5m16s Details / deps (pull_request) Successful in 14s Details / test (pull_request) Successful in 5m19s Details	2024-12-11 23:28:15 -08:00
Jacob Lifshay	8616ee4737	tests/sim: test_enums works! All checks were successful / deps (push) Successful in 17s Details / test (push) Successful in 5m18s Details / deps (pull_request) Successful in 14s Details / test (pull_request) Successful in 5m20s Details	2024-12-11 00:01:04 -08:00
Jacob Lifshay	ca759168ff	tests/sim: add WIP test for enums	2024-12-10 23:37:26 -08:00
Jacob Lifshay	e4cf66adf8	sim: implement memories, still needs testing All checks were successful / deps (push) Successful in 18s Details / test (push) Successful in 5m15s Details / deps (pull_request) Successful in 14s Details / test (pull_request) Successful in 5m20s Details	2024-12-09 23:03:01 -08:00
Jacob Lifshay	259bee39c2	tests/sim: split expected output text into separate files All checks were successful / deps (push) Successful in 18s Details / test (push) Successful in 5m16s Details / deps (pull_request) Successful in 14s Details / test (pull_request) Successful in 5m22s Details	2024-12-05 18:17:13 -08:00
Jacob Lifshay	42afd2da0e	sim: implement enums (except for connecting unequal enum types) Some checks failed / deps (push) Successful in 18s Details / test (push) Has been cancelled Details / deps (pull_request) Successful in 14s Details / test (pull_request) Successful in 5m24s Details	2024-12-04 20:58:39 -08:00
Jacob Lifshay	fd45465d35	sim: add support for registers All checks were successful / deps (push) Successful in 19s Details / test (push) Successful in 5m1s Details / deps (pull_request) Successful in 14s Details / test (pull_request) Successful in 5m0s Details	2024-12-01 20:14:13 -08:00
Jacob Lifshay	5e0548db26	vcd: single bit signals have no spaces in their value changes	2024-12-01 20:12:43 -08:00
Jacob Lifshay	3abba7f9eb	simulating circuits with deduced resets works All checks were successful / deps (push) Successful in 15s Details / test (push) Successful in 4m58s Details / deps (pull_request) Successful in 14s Details / test (pull_request) Successful in 4m58s Details	2024-11-27 23:52:07 -08:00
Jacob Lifshay	11ddbc43c7	writing VCD for combinatorial circuits works! All checks were successful / deps (push) Successful in 15s Details / test (push) Successful in 4m46s Details / deps (pull_request) Successful in 13s Details / test (pull_request) Successful in 4m45s Details	2024-11-20 22:53:54 -08:00
Jacob Lifshay	c4b5d00419	WIP adding VCD output	2024-11-20 22:53:54 -08:00
Jacob Lifshay	09aa9fbc78	wire up simulator trace writing interface	2024-11-20 22:53:54 -08:00
Jacob Lifshay	288a6b71b9	WIP adding VCD output	2024-11-20 22:53:54 -08:00
Jacob Lifshay	0095570f19	simple combinatorial simulation works!	2024-11-20 22:53:54 -08:00
Jacob Lifshay	f54e55a143	Simulation::settle_step() works for simple modules	2024-11-20 22:53:54 -08:00

24 commits