1002 lines
37 KiB
Rust
1002 lines
37 KiB
Rust
// SPDX-License-Identifier: LGPL-3.0-or-later
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// See Notices.txt for copyright information
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use fayalite::{
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int::UIntValue,
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prelude::*,
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sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation},
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util::RcWriter,
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};
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#[hdl_module(outline_generated)]
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pub fn connect_const() {
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#[hdl]
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let o: UInt<8> = m.output();
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connect(o, 5u8);
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}
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#[test]
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fn test_connect_const() {
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let _n = SourceLocation::normalize_files_for_tests();
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let mut sim = Simulation::new(connect_const());
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sim.settle_step();
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let sim_debug = format!("{sim:#?}");
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println!("#######\n{sim_debug}\n#######");
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if sim_debug
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!= r#"Simulation {
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state: State {
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insns: Insns {
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state_layout: StateLayout {
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ty: TypeLayout {
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small_slots: StatePartAllocationLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartAllocationLayout<BigSlots> {
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len: 2,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(connect_const: connect_const).connect_const::o",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<8>,
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},
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],
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..
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},
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},
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},
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insns: [
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// at: module-XXXXXXXXXX.rs:1:1
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Const {
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dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "", ty: UInt<8> },
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value: 5,
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},
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// at: module-XXXXXXXXXX.rs:3:1
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Copy {
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dest: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const: connect_const).connect_const::o", ty: UInt<8> },
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src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "", ty: UInt<8> },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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Return,
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],
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..
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},
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pc: 2,
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small_slots: StatePart {
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value: [],
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},
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big_slots: StatePart {
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value: [
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5,
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5,
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],
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},
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},
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io: Instance {
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name: <simulator>::connect_const,
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instantiated: Module {
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name: connect_const,
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..
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},
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},
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uninitialized_inputs: {},
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io_targets: {
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Instance {
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name: <simulator>::connect_const,
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instantiated: Module {
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name: connect_const,
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..
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},
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}.o: CompiledValue {
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layout: CompiledTypeLayout {
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ty: UInt<8>,
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layout: TypeLayout {
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small_slots: StatePartAllocationLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartAllocationLayout<BigSlots> {
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len: 1,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(connect_const: connect_const).connect_const::o",
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ty: UInt<8>,
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},
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],
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..
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},
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},
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body: Scalar,
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},
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range: TypeIndexRange {
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small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
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big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
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},
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write: None,
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},
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},
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made_initial_step: true,
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trace_decls: TraceModule {
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name: "connect_const",
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children: [
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TraceModuleIO {
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name: "o",
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child: TraceUInt {
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id: TraceScalarId(0),
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name: "o",
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ty: UInt<8>,
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flow: Sink,
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},
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ty: UInt<8>,
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flow: Sink,
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},
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],
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},
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traces: [
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SimTrace {
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id: TraceScalarId(0),
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kind: BigUInt {
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index: StatePartIndex<BigSlots>(0),
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ty: UInt<8>,
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},
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state: 0x05,
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last_state: 0x05,
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},
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],
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trace_writers: [],
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instant: 0 s,
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}"# {
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panic!();
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}
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assert_eq!(sim.read_bool_or_int(sim.io().o), UIntValue::from(5u8));
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}
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#[hdl_module(outline_generated)]
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pub fn mod1_child() {
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#[hdl]
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let i: UInt<4> = m.input();
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#[hdl]
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let o: SInt<2> = m.output();
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#[hdl]
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let i2: SInt<2> = m.input();
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#[hdl]
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let o2: UInt<4> = m.output();
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connect(o, i.cast_to_static());
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connect(o2, i2.cast_to_static());
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#[hdl]
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if i.cmp_gt(5_hdl_u4) {
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connect(o2, 0xF_hdl_u4);
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}
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}
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#[hdl_module(outline_generated)]
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pub fn mod1() {
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#[hdl]
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let child = instance(mod1_child());
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#[hdl]
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let o: mod1_child = m.output(Expr::ty(child));
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connect(o, child);
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}
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#[cfg(todo)]
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#[hdl]
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#[test]
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fn test_mod1() {
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let _n = SourceLocation::normalize_files_for_tests();
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let mut sim = Simulation::new(mod1());
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let mut writer = RcWriter::default();
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sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
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sim.write_bool_or_int(sim.io().o.i, 0x3_hdl_u4);
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sim.write_bool_or_int(sim.io().o.i2, -2_hdl_i2);
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sim.advance_time(SimDuration::from_micros(1));
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sim.write_bool_or_int(sim.io().o.i, 0xA_hdl_u4);
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sim.advance_time(SimDuration::from_micros(1));
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let vcd = String::from_utf8(writer.take()).unwrap();
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println!("####### VCD:\n{vcd}\n#######");
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todo!("generated vcd is incorrect");
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if vcd != r#""# {
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panic!();
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}
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let sim_debug = format!("{sim:#?}");
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println!("#######\n{sim_debug}\n#######");
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if sim_debug
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!= r#"Simulation {
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state: State {
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insns: Insns {
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state_layout: StateLayout {
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ty: TypeLayout {
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small_slots: StatePartAllocationLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartAllocationLayout<BigSlots> {
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len: 17,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::o.i",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::o.o",
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ty: SInt<2>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::o.i2",
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ty: SInt<2>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::o.o2",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::child.i",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::child.o",
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ty: SInt<2>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::child.i2",
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ty: SInt<2>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::child.o2",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o",
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ty: SInt<2>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2",
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ty: SInt<2>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "",
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ty: SInt<2>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: UInt<4>,
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},
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],
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..
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},
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},
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},
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insns: [
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// at: module-XXXXXXXXXX.rs:4:1
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Copy {
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dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
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src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i2", ty: SInt<2> },
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},
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Copy {
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dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i", ty: UInt<4> },
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},
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// at: module-XXXXXXXXXX.rs:2:1
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Copy {
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dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
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src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
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},
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Copy {
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dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
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},
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// at: module-XXXXXXXXXX-2.rs:1:1
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Const {
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dest: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<4> },
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value: 15,
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},
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Const {
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dest: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<4> },
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value: 5,
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},
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CmpLt {
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dest: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: Bool },
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lhs: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<4> },
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rhs: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
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},
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CastToUInt {
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dest: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
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dest_width: 4,
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},
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// at: module-XXXXXXXXXX-2.rs:7:1
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Copy {
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dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<4> },
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},
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// at: module-XXXXXXXXXX-2.rs:8:1
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BranchIfZero {
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target: 11,
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value: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: Bool },
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},
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// at: module-XXXXXXXXXX-2.rs:9:1
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Copy {
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dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<4> },
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},
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// at: module-XXXXXXXXXX.rs:2:1
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Copy {
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dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
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},
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// at: module-XXXXXXXXXX.rs:4:1
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Copy {
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dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o2", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
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},
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// at: module-XXXXXXXXXX-2.rs:1:1
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CastToSInt {
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dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "", ty: SInt<2> },
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src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
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dest_width: 2,
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},
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// at: module-XXXXXXXXXX-2.rs:6:1
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Copy {
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dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
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src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "", ty: SInt<2> },
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},
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// at: module-XXXXXXXXXX.rs:2:1
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Copy {
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dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
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src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
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},
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// at: module-XXXXXXXXXX.rs:4:1
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Copy {
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dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o", ty: SInt<2> },
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src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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Return,
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],
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..
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},
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pc: 17,
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small_slots: StatePart {
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value: [],
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},
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big_slots: StatePart {
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value: [
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10,
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-2,
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-2,
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15,
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10,
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-2,
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-2,
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15,
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10,
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-2,
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-2,
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15,
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-2,
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14,
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5,
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1,
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15,
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],
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},
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},
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io: Instance {
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name: <simulator>::mod1,
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instantiated: Module {
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name: mod1,
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..
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},
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},
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uninitialized_inputs: {},
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io_targets: {
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Instance {
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name: <simulator>::mod1,
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instantiated: Module {
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name: mod1,
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..
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},
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}.o: CompiledValue {
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layout: CompiledTypeLayout {
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ty: Bundle {
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#[hdl(flip)] /* offset = 0 */
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i: UInt<4>,
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/* offset = 4 */
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o: SInt<2>,
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#[hdl(flip)] /* offset = 6 */
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i2: SInt<2>,
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/* offset = 8 */
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o2: UInt<4>,
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},
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layout: TypeLayout {
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small_slots: StatePartAllocationLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartAllocationLayout<BigSlots> {
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len: 4,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::o.i",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::o.o",
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ty: SInt<2>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::o.i2",
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ty: SInt<2>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::o.o2",
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ty: UInt<4>,
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},
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],
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..
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},
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},
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body: Bundle {
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fields: [
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CompiledBundleField {
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offset: TypeIndex {
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small_slots: StatePartIndex<SmallSlots>(0),
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big_slots: StatePartIndex<BigSlots>(0),
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},
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ty: CompiledTypeLayout {
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ty: UInt<4>,
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layout: TypeLayout {
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small_slots: StatePartAllocationLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartAllocationLayout<BigSlots> {
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len: 1,
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debug_data: [
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SlotDebugData {
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name: "",
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ty: UInt<4>,
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},
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],
|
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..
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},
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},
|
|
body: Scalar,
|
|
},
|
|
},
|
|
CompiledBundleField {
|
|
offset: TypeIndex {
|
|
small_slots: StatePartIndex<SmallSlots>(0),
|
|
big_slots: StatePartIndex<BigSlots>(1),
|
|
},
|
|
ty: CompiledTypeLayout {
|
|
ty: SInt<2>,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartAllocationLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartAllocationLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: SInt<2>,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
},
|
|
CompiledBundleField {
|
|
offset: TypeIndex {
|
|
small_slots: StatePartIndex<SmallSlots>(0),
|
|
big_slots: StatePartIndex<BigSlots>(2),
|
|
},
|
|
ty: CompiledTypeLayout {
|
|
ty: SInt<2>,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartAllocationLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartAllocationLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: SInt<2>,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
},
|
|
CompiledBundleField {
|
|
offset: TypeIndex {
|
|
small_slots: StatePartIndex<SmallSlots>(0),
|
|
big_slots: StatePartIndex<BigSlots>(3),
|
|
},
|
|
ty: CompiledTypeLayout {
|
|
ty: UInt<4>,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartAllocationLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartAllocationLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: UInt<4>,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
},
|
|
],
|
|
},
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 4 },
|
|
},
|
|
write: None,
|
|
},
|
|
Instance {
|
|
name: <simulator>::mod1,
|
|
instantiated: Module {
|
|
name: mod1,
|
|
..
|
|
},
|
|
}.o.i: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: UInt<4>,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartAllocationLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartAllocationLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: UInt<4>,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
|
|
},
|
|
write: None,
|
|
},
|
|
Instance {
|
|
name: <simulator>::mod1,
|
|
instantiated: Module {
|
|
name: mod1,
|
|
..
|
|
},
|
|
}.o.i2: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: SInt<2>,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartAllocationLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartAllocationLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: SInt<2>,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
|
|
},
|
|
write: None,
|
|
},
|
|
Instance {
|
|
name: <simulator>::mod1,
|
|
instantiated: Module {
|
|
name: mod1,
|
|
..
|
|
},
|
|
}.o.o: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: SInt<2>,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartAllocationLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartAllocationLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: SInt<2>,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
|
|
},
|
|
write: None,
|
|
},
|
|
Instance {
|
|
name: <simulator>::mod1,
|
|
instantiated: Module {
|
|
name: mod1,
|
|
..
|
|
},
|
|
}.o.o2: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: UInt<4>,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartAllocationLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartAllocationLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: UInt<4>,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
|
|
},
|
|
write: None,
|
|
},
|
|
},
|
|
made_initial_step: true,
|
|
trace_decls: TraceModule {
|
|
name: "mod1",
|
|
children: [
|
|
TraceModuleIO {
|
|
name: "o",
|
|
child: TraceBundle {
|
|
name: "o",
|
|
fields: [
|
|
TraceUInt {
|
|
id: TraceScalarId(0),
|
|
name: "i",
|
|
ty: UInt<4>,
|
|
flow: Source,
|
|
},
|
|
TraceSInt {
|
|
id: TraceScalarId(1),
|
|
name: "o",
|
|
ty: SInt<2>,
|
|
flow: Sink,
|
|
},
|
|
TraceSInt {
|
|
id: TraceScalarId(2),
|
|
name: "i2",
|
|
ty: SInt<2>,
|
|
flow: Source,
|
|
},
|
|
TraceUInt {
|
|
id: TraceScalarId(3),
|
|
name: "o2",
|
|
ty: UInt<4>,
|
|
flow: Sink,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
#[hdl(flip)] /* offset = 0 */
|
|
i: UInt<4>,
|
|
/* offset = 4 */
|
|
o: SInt<2>,
|
|
#[hdl(flip)] /* offset = 6 */
|
|
i2: SInt<2>,
|
|
/* offset = 8 */
|
|
o2: UInt<4>,
|
|
},
|
|
flow: Sink,
|
|
},
|
|
ty: Bundle {
|
|
#[hdl(flip)] /* offset = 0 */
|
|
i: UInt<4>,
|
|
/* offset = 4 */
|
|
o: SInt<2>,
|
|
#[hdl(flip)] /* offset = 6 */
|
|
i2: SInt<2>,
|
|
/* offset = 8 */
|
|
o2: UInt<4>,
|
|
},
|
|
flow: Sink,
|
|
},
|
|
TraceInstance {
|
|
name: "child",
|
|
instance_io: TraceBundle {
|
|
name: "child",
|
|
fields: [
|
|
TraceUInt {
|
|
id: TraceScalarId(8),
|
|
name: "i",
|
|
ty: UInt<4>,
|
|
flow: Sink,
|
|
},
|
|
TraceSInt {
|
|
id: TraceScalarId(9),
|
|
name: "o",
|
|
ty: SInt<2>,
|
|
flow: Source,
|
|
},
|
|
TraceSInt {
|
|
id: TraceScalarId(10),
|
|
name: "i2",
|
|
ty: SInt<2>,
|
|
flow: Sink,
|
|
},
|
|
TraceUInt {
|
|
id: TraceScalarId(11),
|
|
name: "o2",
|
|
ty: UInt<4>,
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
#[hdl(flip)] /* offset = 0 */
|
|
i: UInt<4>,
|
|
/* offset = 4 */
|
|
o: SInt<2>,
|
|
#[hdl(flip)] /* offset = 6 */
|
|
i2: SInt<2>,
|
|
/* offset = 8 */
|
|
o2: UInt<4>,
|
|
},
|
|
flow: Source,
|
|
},
|
|
module: TraceModule {
|
|
name: "mod1_child",
|
|
children: [
|
|
TraceModuleIO {
|
|
name: "i",
|
|
child: TraceUInt {
|
|
id: TraceScalarId(4),
|
|
name: "i",
|
|
ty: UInt<4>,
|
|
flow: Source,
|
|
},
|
|
ty: UInt<4>,
|
|
flow: Source,
|
|
},
|
|
TraceModuleIO {
|
|
name: "o",
|
|
child: TraceSInt {
|
|
id: TraceScalarId(5),
|
|
name: "o",
|
|
ty: SInt<2>,
|
|
flow: Sink,
|
|
},
|
|
ty: SInt<2>,
|
|
flow: Sink,
|
|
},
|
|
TraceModuleIO {
|
|
name: "i2",
|
|
child: TraceSInt {
|
|
id: TraceScalarId(6),
|
|
name: "i2",
|
|
ty: SInt<2>,
|
|
flow: Source,
|
|
},
|
|
ty: SInt<2>,
|
|
flow: Source,
|
|
},
|
|
TraceModuleIO {
|
|
name: "o2",
|
|
child: TraceUInt {
|
|
id: TraceScalarId(7),
|
|
name: "o2",
|
|
ty: UInt<4>,
|
|
flow: Sink,
|
|
},
|
|
ty: UInt<4>,
|
|
flow: Sink,
|
|
},
|
|
],
|
|
},
|
|
ty: Bundle {
|
|
#[hdl(flip)] /* offset = 0 */
|
|
i: UInt<4>,
|
|
/* offset = 4 */
|
|
o: SInt<2>,
|
|
#[hdl(flip)] /* offset = 6 */
|
|
i2: SInt<2>,
|
|
/* offset = 8 */
|
|
o2: UInt<4>,
|
|
},
|
|
},
|
|
],
|
|
},
|
|
traces: [
|
|
SimTrace {
|
|
id: TraceScalarId(0),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(0),
|
|
ty: UInt<4>,
|
|
},
|
|
state: 0xa,
|
|
last_state: 0xa,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(1),
|
|
kind: BigSInt {
|
|
index: StatePartIndex<BigSlots>(1),
|
|
ty: SInt<2>,
|
|
},
|
|
state: 0x2,
|
|
last_state: 0x2,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(2),
|
|
kind: BigSInt {
|
|
index: StatePartIndex<BigSlots>(2),
|
|
ty: SInt<2>,
|
|
},
|
|
state: 0x2,
|
|
last_state: 0x2,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(3),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(3),
|
|
ty: UInt<4>,
|
|
},
|
|
state: 0xf,
|
|
last_state: 0xf,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(4),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(8),
|
|
ty: UInt<4>,
|
|
},
|
|
state: 0xa,
|
|
last_state: 0xa,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(5),
|
|
kind: BigSInt {
|
|
index: StatePartIndex<BigSlots>(9),
|
|
ty: SInt<2>,
|
|
},
|
|
state: 0x2,
|
|
last_state: 0x2,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(6),
|
|
kind: BigSInt {
|
|
index: StatePartIndex<BigSlots>(10),
|
|
ty: SInt<2>,
|
|
},
|
|
state: 0x2,
|
|
last_state: 0x2,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(7),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(11),
|
|
ty: UInt<4>,
|
|
},
|
|
state: 0xf,
|
|
last_state: 0xf,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(8),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(4),
|
|
ty: UInt<4>,
|
|
},
|
|
state: 0xa,
|
|
last_state: 0xa,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(9),
|
|
kind: BigSInt {
|
|
index: StatePartIndex<BigSlots>(5),
|
|
ty: SInt<2>,
|
|
},
|
|
state: 0x2,
|
|
last_state: 0x2,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(10),
|
|
kind: BigSInt {
|
|
index: StatePartIndex<BigSlots>(6),
|
|
ty: SInt<2>,
|
|
},
|
|
state: 0x2,
|
|
last_state: 0x2,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(11),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(7),
|
|
ty: UInt<4>,
|
|
},
|
|
state: 0xf,
|
|
last_state: 0xf,
|
|
},
|
|
],
|
|
trace_writers: [],
|
|
instant: 0 s,
|
|
}"# {
|
|
panic!();
|
|
}
|
|
let expected = -2_hdl_i2;
|
|
assert_eq!(sim.read_bool_or_int(sim.io().o.o).to_expr(), expected);
|
|
let expected = 0xF_hdl_u4;
|
|
assert_eq!(sim.read_bool_or_int(sim.io().o.o2).to_expr(), expected);
|
|
}
|