…
..
dynamic_part_select
.gitignore
abc9.v
abc9.ys
abstract_init.ys	abstract: test -slice from:to for -init	2025-02-25 00:22:14 +01:00
abstract_state.ys	abstract: test -slice for all modes, -rtlilslice for -init	2025-02-25 00:18:16 +01:00
abstract_value.ys	abstract: test -slice for all modes, -rtlilslice for -init	2025-02-25 00:18:16 +01:00
aiger2.ys
aiger_dff.ys
async.sh
async.v
attrib05_port_conn.v
attrib05_port_conn.ys
attrib07_func_call.v
attrib07_func_call.ys
autoname.ys
blackbox_wb.ys
box_derive.ys
bug1496.ys
bug1531.ys
bug1614.ys
bug1710.ys
bug1745.ys
bug1781.ys
bug1876.ys	tests: add testcases from #1876	2020-04-14 12:39:10 -07:00
bug2014.ys
bug3462.ys
bug3879.ys
bug4082.ys	rtlil: Add wire deletion test	2024-01-29 11:25:54 +01:00
bug4865.ys	ice40_dsp: fix test	2025-03-26 15:13:05 +02:00
bug4909.ys
cellarray_array_connections.ys
celledges_shift.ys
check.ys
check_2.ys
check_3.ys
check_4.ys
chformal_check.ys
chformal_coverenable.ys
chparam.sh
clk2fflogic_effects.sh	clk2fflogic: Fix handling of $check cells	2024-02-14 11:42:27 +01:00
clk2fflogic_effects.sv
const_arg_loop.sv
const_arg_loop.ys
const_func.sv
const_func.ys
const_func_block_var.v
const_func_block_var.ys	Allow blocks with declarations within constant functions	2020-07-25 10:16:12 -06:00
constant_drive_conflict.ys
constcomment.ys
constmsk_test.v
constmsk_test.ys
constmsk_testmap.v
countbits.sv
countbits.ys
cutpoint_blackbox.ys
cutpoint_whole.ys
deminout_unused.ys
design.ys
design1.ys
design2.ys
dynamic_part_select.ys	Add torture test for (* nowrshmsk *) stride optimization	2024-01-10 20:28:36 +01:00
elab_sys_tasks.sv
elab_sys_tasks.ys	Initial implementation of elaboration system tasks	2019-05-03 03:10:43 +03:00
equiv_make_make_assert.ys
equiv_opt_multiclock.ys	Add equiv_opt -multiclock	2019-09-11 13:55:59 +01:00
equiv_opt_undef.ys
exec.ys	Add test for exec command.	2020-03-16 07:52:58 +00:00
fib.v
fib.ys	verilog: improved support for recursive functions	2020-12-31 18:33:59 -07:00
fib_tern.v	verilog: support recursive functions using ternary expressions	2021-02-12 14:43:42 -05:00
fib_tern.ys
formalff_declockgate.ys
func_port_implied_dir.sv	sv: complete support for implied task/function port directions	2020-12-31 16:17:13 -07:00
func_port_implied_dir.ys
gen_if_null.v
gen_if_null.ys
global_scope.ys	ast: Fix handling of identifiers in the global scope	2020-04-16 10:30:07 +01:00
gzip_verilog.v.gz
gzip_verilog.ys
help.ys
hierarchy.sh
hierarchy_defer.ys	Expand test with `hierarchy' without -auto-top	2019-09-03 12:17:26 -07:00
hierarchy_generate.ys
hierarchy_param.ys
ice40_mince_abc9.ys
integer_range_bad_syntax.ys
integer_real_bad_syntax.ys
json_escape_chars.ys	fix handling of escaped chars in json backend and frontend	2022-02-18 17:13:09 +01:00
json_scopeinfo.ys
keep_hierarchy.ys
logger_cmd_error.sh
logger_error.ys
logger_fail.sh
logger_nowarning.ys
logger_warn.ys
logger_warning.ys
logic_param_simple.ys
mem2reg.ys
memory_word_as_index.data
memory_word_as_index.v
memory_word_as_index.ys
muxcover.ys
muxpack.v
muxpack.ys	More deadname stuff	2021-06-09 12:40:33 +02:00
param_struct.ys	tests: Run async2sync before sat and/or sim to handle $check cells	2024-02-01 16:14:11 +01:00
peepopt.ys
peepopt_formal.ys
plugin.cc
plugin.sh
pmgen_reduce.ys
pmux2shiftx.v
pmux2shiftx.ys
port_sign_extend.v
port_sign_extend.ys
primitives.ys
printattr.ys
rand_const.sv
rand_const.ys
reg_wire_error.sv
reg_wire_error.ys	reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files	2018-06-05 18:00:06 +03:00
rename_scramble_name.ys
rtlil_signed_attribute.ys
rtlil_z_bits.ys
run-test.sh
scopeinfo.ys
scratchpad.ys
script.ys
setundef.sv
setundef.ys
sformatf.ys	ast: use new format string helpers.	2023-08-11 04:46:52 +02:00
shregmap.v
shregmap.ys
signed.ys
signext.ys
sim_const.ys
specify.v
specify.ys	verilog: fix specify src attribute	2020-05-04 10:53:06 -07:00
src.ys	verilog: add test	2020-03-11 06:51:03 -07:00
sta.ys
stat.ys
struct_access.sv
struct_access.ys
sub.v
submod.ys	Add a quick testcase for unknown modules as inout	2019-12-09 13:14:46 -08:00
submod_extract.ys
sv_defines.ys
sv_defines_dup.ys
sv_defines_mismatch.ys
sv_defines_too_few.ys
sv_implicit_ports.sh
svalways.sh
tcl_apis.tcl
tcl_apis.v	Redo integer passing on top of bignum	2024-12-02 19:56:51 +01:00
tcl_apis.ys	Fix test	2024-11-04 16:19:59 +01:00
wrapcell.ys
wreduce.ys
wreduce2.ys
write_gzip.ys
xaiger.ys