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https://github.com/YosysHQ/yosys
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cutpoint.cc: Fold -instances into -blackbox
Replace `cutpoint -blackbox` behaviour with `cutpoint -blackbox -instances` behaviour. Drop `-instances` flag. Add `-noscopeinfo` flag. Use `RTLIL::Selection::boxed_module()` helper to shortcut blackbox check. Update `cutpoint_blackbox.ys` tests to match.
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@ -37,19 +37,20 @@ struct CutpointPass : public Pass {
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log(" set cutpoint nets to undef (x). the default behavior is to create\n");
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log(" an $anyseq cell and drive the cutpoint net from that\n");
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log("\n");
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log(" -noscopeinfo\n");
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log(" do not create '$scopeinfo' cells that preserve attributes of cells that\n");
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log(" were removed by this pass\n");
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log("\n");
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log(" cutpoint -blackbox [options]\n");
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log("\n");
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log("Replace the contents of all blackboxes in the design with a formal cut point.\n");
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log("\n");
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log(" -instances\n");
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log(" replace instances of blackboxes instead of the modules\n");
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log("Replace all instances of blackboxes in the design with a formal cut point.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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bool flag_undef = false;
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bool flag_scopeinfo = true;
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bool flag_blackbox = false;
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bool flag_instances = false;
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log_header(design, "Executing CUTPOINT pass.\n");
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@ -60,61 +61,31 @@ struct CutpointPass : public Pass {
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flag_undef = true;
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continue;
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}
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if (args[argidx] == "-blackbox") {
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flag_blackbox = true;
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if (args[argidx] == "-noscopeinfo") {
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flag_scopeinfo = false;
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continue;
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}
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if (args[argidx] == "-instances") {
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flag_instances = true;
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if (args[argidx] == "-blackbox") {
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flag_blackbox = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (flag_instances && !flag_blackbox) {
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log_cmd_error("-instances flag only valid with -blackbox!\n");
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}
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if (flag_blackbox) {
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if (!design->full_selection())
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log_cmd_error("This command only operates on fully selected designs!\n");
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design->push_empty_selection();
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auto &selection = design->selection();
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for (auto module : design->modules())
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if (flag_instances) {
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for (auto cell : module->cells()) {
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auto mod = design->module(cell->type);
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if (mod != nullptr && mod->get_blackbox_attribute())
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design->select(module, cell);
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}
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} else {
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if (module->get_blackbox_attribute())
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design->select(module);
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}
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for (auto cell : module->cells())
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if (selection.boxed_module(cell->type))
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selection.select(module, cell);
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}
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for (auto module : design->all_selected_modules())
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{
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if (module->is_selected_whole() && !flag_instances) {
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log("Making all outputs of module %s cut points, removing module contents.\n", log_id(module));
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module->new_connections(std::vector<RTLIL::SigSig>());
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for (auto cell : vector<Cell*>(module->cells()))
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module->remove(cell);
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vector<Wire*> output_wires;
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for (auto wire : module->wires())
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if (wire->port_output)
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output_wires.push_back(wire);
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for (auto wire : output_wires)
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module->connect(wire, flag_undef ? Const(State::Sx, GetSize(wire)) : module->Anyseq(NEW_ID, GetSize(wire)));
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if (module->get_blackbox_attribute()) {
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module->set_bool_attribute(ID::blackbox, false);
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module->set_bool_attribute(ID::whitebox, false);
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auto scopeinfo = module->addCell(NEW_ID, ID($scopeinfo));
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scopeinfo->setParam(ID::TYPE, RTLIL::Const("blackbox"));
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}
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continue;
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}
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SigMap sigmap(module);
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pool<SigBit> cutpoint_bits;
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@ -129,7 +100,7 @@ struct CutpointPass : public Pass {
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RTLIL::Cell *scopeinfo = nullptr;
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auto cell_name = cell->name;
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if (flag_instances && cell_name.isPublic()) {
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if (flag_scopeinfo && cell_name.isPublic()) {
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auto scopeinfo = module->addCell(NEW_ID, ID($scopeinfo));
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scopeinfo->setParam(ID::TYPE, RTLIL::Const("blackbox"));
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@ -28,20 +28,25 @@ EOT
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hierarchy -top top
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design -save hier
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select -assert-count 0 t:$anyseq
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select -assert-none t:$anyseq
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select -assert-count 3 =t:?b
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cutpoint -blackbox
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select -assert-count 3 =t:?b
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select -assert-count 2 r:SOME_PARAM
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select -assert-count 1 r:SOME_PARAM=1
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select -assert-none =t:?b
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select -assert-none r:SOME_PARAM
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flatten
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select -assert-count 3 t:$anyseq
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select -assert-count 3 t:$scopeinfo
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select -assert-count 3 t:$scopeinfo r:TYPE=blackbox %i
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select -assert-count 3 t:$scopeinfo n:*cutpoint.cc* %i
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# cutpoint -blackbox === cutpoint =A:whitebox =A:blackbox %u
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# (simplified to =A:*box)
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# -noscopeinfo works with -blackbox
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design -load hier
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cutpoint -blackbox -noscopeinfo
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select -assert-none t:$scopeinfo
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# cutpoint -blackbox === cutpoint =A:whitebox =A:blackbox %u %C
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# (simplified to =A:*box %C)
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design -load hier
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cutpoint -blackbox
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rename -enumerate -pattern A_% t:$scopeinfo
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@ -50,33 +55,6 @@ rename -enumerate -pattern C_% w:*Anyseq*
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design -save gold
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select -write cutpoint.gold.sel =*
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design -load hier
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cutpoint =A:*box
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rename -enumerate -pattern A_% t:$scopeinfo
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rename -enumerate -pattern B_% t:$anyseq
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rename -enumerate -pattern C_% w:*Anyseq*
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design -save gate
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select -write cutpoint.gate.sel
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select -read cutpoint.gold.sel
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# nothing in gate but not gold
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select -assert-none % %n
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design -load gold
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select -read cutpoint.gate.sel
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# nothing in gold but not gate
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select -assert-none % %n
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# cutpoint -blackbox -instances !== cutpoint =A:whitebox =A:blackbox %u %C
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# (simplified to =A:*box %C)
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# because cutpoint -blackbox -instances adds $scopeinfo cells
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design -load hier
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cutpoint -blackbox -instances
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rename -enumerate -pattern A_% t:$scopeinfo
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rename -enumerate -pattern B_% t:$anyseq
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rename -enumerate -pattern C_% w:*Anyseq*
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design -save gold
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select -write cutpoint.gold.sel =*
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design -load hier
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cutpoint =A:*box %C
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rename -enumerate -pattern A_% t:$scopeinfo
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@ -90,6 +68,5 @@ select -assert-none % %n
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design -load gold
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select -read cutpoint.gate.sel
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# 3 $scopeinfo in gold but not gate
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select -assert-count 3 % %n
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select -assert-count 3 t:$scopeinfo
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# nothing in gold but not gate
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select -assert-none % %n
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