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Add test for bug 3462

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Miodrag Milanovic 2022-08-29 10:10:09 +02:00
parent 4bc1e1d1f1
commit 5b5fe76966
2 changed files with 15 additions and 0 deletions
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12
tests/various/bug3462.ys Normal file
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read_verilog <<EOT
module top();
wire array[0:0];
wire out;
sub #(.d(1)) inst(
.in(array[0]),
.out(out)
);
endmodule
EOT
hierarchy -top top -libdir .

3
tests/various/sub.v Normal file
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module sub #(parameter d=1) (input in, output out);
assign out = in;
endmodule