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rtlil: Add wire deletion test

This commit is contained in:
Martin Povišer 2024-01-22 14:42:45 +01:00
parent c035289383
commit ea3dc7c1b4

8
tests/various/bug4082.ys Normal file
View file

@ -0,0 +1,8 @@
read_verilog <<EOF
module top;
wire a;
wire b;
assign a = b;
endmodule
EOF
delete w:a