| .. |
|
dynamic_part_select
|
Add torture test for (* nowrshmsk *) stride optimization
|
2024-01-10 20:28:36 +01:00 |
|
.gitignore
|
|
|
|
abc9.v
|
Another sloppy mistake!
|
2019-11-21 16:33:20 -08:00 |
|
abc9.ys
|
abc9: uniquify blackboxes like whiteboxes (#2695)
|
2021-03-29 22:02:06 -07:00 |
|
abstract_init.ys
|
|
|
|
abstract_state.ys
|
abstract: test -slice for all modes, -rtlilslice for -init
|
2025-02-25 00:18:16 +01:00 |
|
abstract_value.ys
|
abstract: test -slice for all modes, -rtlilslice for -init
|
2025-02-25 00:18:16 +01:00 |
|
aiger2.ys
|
aiger2: Add test of writing a flattened view
|
2024-10-07 12:04:33 +02:00 |
|
aiger_dff.ys
|
write_aiger: Fix non-$_FF_ FFs
|
2022-08-18 13:56:22 +02:00 |
|
async.sh
|
|
|
|
async.v
|
Fix tests/various/async FFL test
|
2019-07-09 22:44:39 +02:00 |
|
attrib05_port_conn.v
|
Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
|
2019-06-04 10:42:42 +02:00 |
|
attrib05_port_conn.ys
|
|
|
|
attrib07_func_call.v
|
|
|
|
attrib07_func_call.ys
|
Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
|
2019-06-04 10:42:42 +02:00 |
|
autoname.ys
|
Remove references to ilang
|
2024-11-05 12:36:31 +13:00 |
|
blackbox_wb.ys
|
blackbox: Include whiteboxed modules
|
2021-03-17 13:58:04 +00:00 |
|
box_derive.ys
|
|
|
|
bug1496.ys
|
|
|
|
bug1531.ys
|
|
|
|
bug1614.ys
|
add testcase for #1614
|
2020-02-03 21:29:54 +01:00 |
|
bug1710.ys
|
ast: fixes #1710; do not generate RTLIL for unreachable ternary
|
2020-02-27 16:55:55 -08:00 |
|
bug1745.ys
|
|
|
|
bug1781.ys
|
fsm_extract: Initialize celltypes with full design.
|
2020-03-19 18:51:21 +01:00 |
|
bug1876.ys
|
tests: add testcases from #1876
|
2020-04-14 12:39:10 -07:00 |
|
bug2014.ys
|
|
|
|
bug3462.ys
|
Add test for bug 3462
|
2022-08-29 10:10:09 +02:00 |
|
bug3879.ys
|
extract_fa: Add test case
|
2025-01-30 18:45:06 +01:00 |
|
bug4082.ys
|
rtlil: Add wire deletion test
|
2024-01-29 11:25:54 +01:00 |
|
bug4865.ys
|
|
|
|
bug4909.ys
|
|
|
|
cellarray_array_connections.ys
|
simplify: regression test for AST_CELLARRAY simplification issue
|
2022-12-07 18:41:55 +01:00 |
|
celledges_shift.ys
|
celledges: Add test of shift cells edge data
|
2024-01-19 11:14:10 +01:00 |
|
check.ys
|
|
|
|
check_2.ys
|
check: Extend testing
|
2024-03-11 10:45:17 +01:00 |
|
check_3.ys
|
|
|
|
check_4.ys
|
|
|
|
chformal_check.ys
|
|
|
|
chformal_coverenable.ys
|
|
|
|
chparam.sh
|
tests: Run async2sync before sat and/or sim to handle $check cells
|
2024-02-01 16:14:11 +01:00 |
|
clk2fflogic_effects.sh
|
|
|
|
clk2fflogic_effects.sv
|
|
|
|
const_arg_loop.sv
|
verilog: fix sizing of constant args for tasks/functions
|
2021-02-21 15:44:43 -05:00 |
|
const_arg_loop.ys
|
tests: Run async2sync before sat and/or sim to handle $check cells
|
2024-02-01 16:14:11 +01:00 |
|
const_func.sv
|
verilog: fix sizing of constant args for tasks/functions
|
2021-02-21 15:44:43 -05:00 |
|
const_func.ys
|
|
|
|
const_func_block_var.v
|
|
|
|
const_func_block_var.ys
|
Allow blocks with declarations within constant functions
|
2020-07-25 10:16:12 -06:00 |
|
constant_drive_conflict.ys
|
|
|
|
constcomment.ys
|
|
|
|
constmsk_test.v
|
Added tests/various/constmsk_test.ys
|
2014-09-04 15:07:30 +02:00 |
|
constmsk_test.ys
|
Added tests/various/constmsk_test.ys
|
2014-09-04 15:07:30 +02:00 |
|
constmsk_testmap.v
|
|
|
|
countbits.sv
|
|
|
|
countbits.ys
|
tests: Run async2sync before sat and/or sim to handle $check cells
|
2024-02-01 16:14:11 +01:00 |
|
cutpoint_blackbox.ys
|
|
|
|
cutpoint_whole.ys
|
cutpoint: Re-add whole module optimization
|
2025-05-06 09:57:34 +12:00 |
|
deminout_unused.ys
|
deminout: Don't demote inouts with unused bits
|
2020-03-04 18:44:38 +00:00 |
|
design.ys
|
design: add test
|
2020-04-16 12:48:40 -07:00 |
|
design1.ys
|
design: add test
|
2020-04-16 12:48:40 -07:00 |
|
design2.ys
|
|
|
|
dynamic_part_select.ys
|
|
|
|
elab_sys_tasks.sv
|
|
|
|
elab_sys_tasks.ys
|
Initial implementation of elaboration system tasks
|
2019-05-03 03:10:43 +03:00 |
|
equiv_make_make_assert.ys
|
equiv_make: Add -make_assert option
|
2022-06-24 00:17:02 +01:00 |
|
equiv_opt_multiclock.ys
|
Add equiv_opt -multiclock
|
2019-09-11 13:55:59 +01:00 |
|
equiv_opt_undef.ys
|
Remove references to ilang
|
2024-11-05 12:36:31 +13:00 |
|
exec.ys
|
Add test for exec command.
|
2020-03-16 07:52:58 +00:00 |
|
fib.v
|
|
|
|
fib.ys
|
verilog: improved support for recursive functions
|
2020-12-31 18:33:59 -07:00 |
|
fib_tern.v
|
|
|
|
fib_tern.ys
|
|
|
|
formalff_declockgate.ys
|
|
|
|
func_port_implied_dir.sv
|
sv: complete support for implied task/function port directions
|
2020-12-31 16:17:13 -07:00 |
|
func_port_implied_dir.ys
|
sv: complete support for implied task/function port directions
|
2020-12-31 16:17:13 -07:00 |
|
gen_if_null.v
|
verilog: significant block scoping improvements
|
2021-01-31 09:42:09 -05:00 |
|
gen_if_null.ys
|
|
|
|
global_scope.ys
|
ast: Fix handling of identifiers in the global scope
|
2020-04-16 10:30:07 +01:00 |
|
gzip_verilog.v.gz
|
|
|
|
gzip_verilog.ys
|
Add support for reading gzip'd input files
|
2019-07-26 10:23:58 +01:00 |
|
help.ys
|
tests: Fix invocation of 'help -cells'
|
2023-07-10 12:42:09 +02:00 |
|
hierarchy.sh
|
|
|
|
hierarchy_defer.ys
|
Expand test with `hierarchy' without -auto-top
|
2019-09-03 12:17:26 -07:00 |
|
hierarchy_generate.ys
|
add command that should not have any effect to hierarchy -generate test (this documents the current behavior, not sure if it is desired functionality)
|
2024-04-12 13:51:06 +02:00 |
|
hierarchy_param.ys
|
hierarchy: Convert positional parameters to named.
|
2020-04-21 19:09:00 +02:00 |
|
ice40_mince_abc9.ys
|
|
|
|
integer_range_bad_syntax.ys
|
Revert "Revert PRs #2203 and #2244."
|
2020-07-10 09:59:48 +02:00 |
|
integer_real_bad_syntax.ys
|
|
|
|
json_escape_chars.ys
|
|
|
|
json_scopeinfo.ys
|
|
|
|
keep_hierarchy.ys
|
Add keep_hierarchy test
|
2024-11-05 09:28:45 +01:00 |
|
logger_cmd_error.sh
|
Add test of error not getting silenced
|
2024-10-07 14:49:17 +02:00 |
|
logger_error.ys
|
Added back tests for logger
|
2020-03-13 15:00:18 +01:00 |
|
logger_fail.sh
|
tests: use /usr/bin/env for bash.
|
2023-08-12 11:59:39 +10:00 |
|
logger_nowarning.ys
|
Added back tests for logger
|
2020-03-13 15:00:18 +01:00 |
|
logger_warn.ys
|
Added back tests for logger
|
2020-03-13 15:00:18 +01:00 |
|
logger_warning.ys
|
Added back tests for logger
|
2020-03-13 15:00:18 +01:00 |
|
logic_param_simple.ys
|
Revert "Revert PRs #2203 and #2244."
|
2020-07-10 09:59:48 +02:00 |
|
mem2reg.ys
|
|
|
|
memory_word_as_index.data
|
Fix elaboration of whole memory words used as indices
|
2020-12-26 21:47:38 -07:00 |
|
memory_word_as_index.v
|
Fix elaboration of whole memory words used as indices
|
2020-12-26 21:47:38 -07:00 |
|
memory_word_as_index.ys
|
|
|
|
muxcover.ys
|
muxcover: do not add decode muxes with x inputs
|
2023-01-26 05:19:45 +00:00 |
|
muxpack.v
|
|
|
|
muxpack.ys
|
|
|
|
param_struct.ys
|
tests: Run async2sync before sat and/or sim to handle $check cells
|
2024-02-01 16:14:11 +01:00 |
|
peepopt.ys
|
peepopt: Fix padding for the peepopt_shiftmul_right pattern
|
2023-12-06 18:35:44 +01:00 |
|
peepopt_formal.ys
|
|
|
|
plugin.cc
|
Use C++11 final/override keywords.
|
2020-06-18 23:34:52 +00:00 |
|
plugin.sh
|
|
|
|
pmgen_reduce.ys
|
Add test for pmtest_test "reduce" demo pattern
|
2019-08-17 14:05:10 +02:00 |
|
pmux2shiftx.v
|
|
|
|
pmux2shiftx.ys
|
|
|
|
port_sign_extend.v
|
genrtlil: fix signed port connection codegen failures
|
2021-02-05 19:51:30 -05:00 |
|
port_sign_extend.ys
|
|
|
|
primitives.ys
|
tests: add tests for primitives' src
|
2020-05-04 10:21:47 -07:00 |
|
printattr.ys
|
printattrs: Add test.
|
2020-05-27 08:00:00 +00:00 |
|
rand_const.sv
|
|
|
|
rand_const.ys
|
Allow combination of rand and const modifiers
|
2021-01-21 08:42:05 -07:00 |
|
reg_wire_error.sv
|
Modified errors into warnings
|
2018-06-05 18:03:22 +03:00 |
|
reg_wire_error.ys
|
|
|
|
rename_scramble_name.ys
|
|
|
|
rename_unescape.ys
|
|
|
|
rtlil_signed_attribute.ys
|
Ensure signed constants are correctly parsed, represented, and exported in RTLIL. Add a test to check parsing and exporting
|
2024-08-21 14:28:42 +01:00 |
|
rtlil_z_bits.ys
|
backends/rtlil: Do not shorten a value with z bits to 'x
|
2023-01-29 14:02:25 +01:00 |
|
run-test.sh
|
test: restore verific handling, nicer naming
|
2024-12-13 10:24:47 +01:00 |
|
scopeinfo.ys
|
Test flatten and opt_clean's $scopeinfo handling
|
2024-02-06 17:51:29 +01:00 |
|
scratchpad.ys
|
add assert option to scratchpad command
|
2019-12-16 14:00:21 +01:00 |
|
script.ys
|
|
|
|
setundef.sv
|
|
|
|
setundef.ys
|
Fix setting bits of parameters in setundef pass
|
2024-11-08 17:03:08 +01:00 |
|
sformatf.ys
|
|
|
|
shregmap.v
|
tests: fix some test warnings
|
2020-05-25 10:07:58 -07:00 |
|
shregmap.ys
|
|
|
|
signed.ys
|
Revert "Revert PRs #2203 and #2244."
|
2020-07-10 09:59:48 +02:00 |
|
signext.ys
|
|
|
|
sim_const.ys
|
|
|
|
specify.v
|
verilog: ignore ranges too without -specify
|
2020-02-13 17:58:43 -08:00 |
|
specify.ys
|
|
|
|
splitnets.ys
|
|
|
|
src.ys
|
|
|
|
sta.ys
|
|
|
|
stat.ys
|
create testcase to check correct addition of areas.
|
2025-04-20 16:44:22 +02:00 |
|
struct_access.sv
|
Fix access to whole sub-structs (#3086)
|
2022-02-14 14:34:20 +01:00 |
|
struct_access.ys
|
tests: Run async2sync before sat and/or sim to handle $check cells
|
2024-02-01 16:14:11 +01:00 |
|
sub.v
|
|
|
|
submod.ys
|
Add a quick testcase for unknown modules as inout
|
2019-12-09 13:14:46 -08:00 |
|
submod_extract.ys
|
|
|
|
sv_defines.ys
|
Add support for SystemVerilog-style `define to Verilog frontend
|
2020-03-27 16:08:26 +00:00 |
|
sv_defines_dup.ys
|
Add support for SystemVerilog-style `define to Verilog frontend
|
2020-03-27 16:08:26 +00:00 |
|
sv_defines_mismatch.ys
|
Add support for SystemVerilog-style `define to Verilog frontend
|
2020-03-27 16:08:26 +00:00 |
|
sv_defines_too_few.ys
|
|
|
|
sv_implicit_ports.sh
|
tests: use /usr/bin/env for bash.
|
2023-08-12 11:59:39 +10:00 |
|
svalways.sh
|
tests: use /usr/bin/env for bash.
|
2023-08-12 11:59:39 +10:00 |
|
tcl_apis.tcl
|
Redo integer passing on top of bignum
|
2024-12-02 19:56:51 +01:00 |
|
tcl_apis.v
|
|
|
|
tcl_apis.ys
|
Fix test
|
2024-11-04 16:19:59 +01:00 |
|
wrapcell.ys
|
wrapcell: Test check -assert post wrapping
|
2024-12-10 15:13:31 +01:00 |
|
wreduce.ys
|
|
|
|
wreduce2.ys
|
|
|
|
write_gzip.ys
|
Do not use Verific in tests/various/write_gzip.ys
|
2019-08-16 14:22:46 +02:00 |
|
xaiger.ys
|
xaiger: add testcase
|
2020-05-24 08:48:23 -07:00 |