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yosys/tests/various
Emil J 6a2f2f1818
Merge pull request #5031 from suisseWalter/fix_sequential_area
stat: fix sequential area not being included in addition/multiplication
2025-04-21 11:02:40 +02:00
..
dynamic_part_select
.gitignore
abc9.v
abc9.ys abc9: uniquify blackboxes like whiteboxes (#2695) 2021-03-29 22:02:06 -07:00
abstract_init.ys
abstract_state.ys
abstract_value.ys
aiger2.ys aiger2: Add test of writing a flattened view 2024-10-07 12:04:33 +02:00
aiger_dff.ys
async.sh
async.v
attrib05_port_conn.v
attrib05_port_conn.ys
attrib07_func_call.v
attrib07_func_call.ys
autoname.ys
blackbox_wb.ys
box_derive.ys box_derive: Tune the test 2024-05-29 20:42:11 +02:00
bug1496.ys Remove references to ilang 2024-11-05 12:36:31 +13:00
bug1531.ys Add testcase 2019-12-11 16:52:37 -08:00
bug1614.ys
bug1710.ys
bug1745.ys Add regression tests for new handling of comments in constants 2020-03-14 11:41:09 +01:00
bug1781.ys
bug1876.ys tests: add testcases from #1876 2020-04-14 12:39:10 -07:00
bug2014.ys test: add test for #2014 2020-05-02 14:22:37 -07:00
bug3462.ys Add test for bug 3462 2022-08-29 10:10:09 +02:00
bug3879.ys
bug4082.ys
bug4865.ys
bug4909.ys
cellarray_array_connections.ys simplify: regression test for AST_CELLARRAY simplification issue 2022-12-07 18:41:55 +01:00
celledges_shift.ys
check.ys check: Extend testing 2024-03-11 10:45:17 +01:00
check_2.ys check: Extend testing 2024-03-11 10:45:17 +01:00
check_3.ys check: Rephrase regex for portability 2024-03-11 10:45:17 +01:00
check_4.ys
chformal_check.ys Additional tests for FV $check compatibility 2024-02-02 16:07:10 +01:00
chformal_coverenable.ys
chparam.sh tests: Run async2sync before sat and/or sim to handle $check cells 2024-02-01 16:14:11 +01:00
clk2fflogic_effects.sh clk2fflogic: Fix handling of $check cells 2024-02-14 11:42:27 +01:00
clk2fflogic_effects.sv clk2fflogic: Fix handling of $check cells 2024-02-14 11:42:27 +01:00
const_arg_loop.sv
const_arg_loop.ys tests: Run async2sync before sat and/or sim to handle $check cells 2024-02-01 16:14:11 +01:00
const_func.sv verilog: fix sizing of constant args for tasks/functions 2021-02-21 15:44:43 -05:00
const_func.ys
const_func_block_var.v
const_func_block_var.ys Allow blocks with declarations within constant functions 2020-07-25 10:16:12 -06:00
constant_drive_conflict.ys check: Also check for conflicts with constant drivers 2023-06-23 18:07:28 +02:00
constcomment.ys Add regression tests for new handling of comments in constants 2020-03-14 11:41:09 +01:00
constmsk_test.v
constmsk_test.ys
constmsk_testmap.v tests: fix some test warnings 2020-05-25 10:07:58 -07:00
countbits.sv
countbits.ys tests: Run async2sync before sat and/or sim to handle $check cells 2024-02-01 16:14:11 +01:00
cutpoint_blackbox.ys
deminout_unused.ys
design.ys design: add test 2020-04-16 12:48:40 -07:00
design1.ys
design2.ys
dynamic_part_select.ys Add torture test for (* nowrshmsk *) stride optimization 2024-01-10 20:28:36 +01:00
elab_sys_tasks.sv Initial implementation of elaboration system tasks 2019-05-03 03:10:43 +03:00
elab_sys_tasks.ys
equiv_make_make_assert.ys
equiv_opt_multiclock.ys
equiv_opt_undef.ys Remove references to ilang 2024-11-05 12:36:31 +13:00
exec.ys Add test for exec command. 2020-03-16 07:52:58 +00:00
fib.v
fib.ys verilog: improved support for recursive functions 2020-12-31 18:33:59 -07:00
fib_tern.v
fib_tern.ys
func_port_implied_dir.sv
func_port_implied_dir.ys sv: complete support for implied task/function port directions 2020-12-31 16:17:13 -07:00
gen_if_null.v
gen_if_null.ys
global_scope.ys ast: Fix handling of identifiers in the global scope 2020-04-16 10:30:07 +01:00
gzip_verilog.v.gz Add support for reading gzip'd input files 2019-07-26 10:23:58 +01:00
gzip_verilog.ys
help.ys
hierarchy.sh
hierarchy_defer.ys
hierarchy_generate.ys add command that should not have any effect to hierarchy -generate test (this documents the current behavior, not sure if it is desired functionality) 2024-04-12 13:51:06 +02:00
hierarchy_param.ys
ice40_mince_abc9.ys
integer_range_bad_syntax.ys
integer_real_bad_syntax.ys Revert "Revert PRs #2203 and #2244." 2020-07-10 09:59:48 +02:00
json_escape_chars.ys
json_scopeinfo.ys emit $scopeinfo cells by default 2025-01-08 14:47:46 +01:00
keep_hierarchy.ys
logger_cmd_error.sh Add test of error not getting silenced 2024-10-07 14:49:17 +02:00
logger_error.ys Added back tests for logger 2020-03-13 15:00:18 +01:00
logger_fail.sh
logger_nowarning.ys
logger_warn.ys
logger_warning.ys Added back tests for logger 2020-03-13 15:00:18 +01:00
logic_param_simple.ys
mem2reg.ys Change attribute search value to specify precise location instead of simple line number. 2020-02-24 01:39:36 +00:00
memory_word_as_index.data Fix elaboration of whole memory words used as indices 2020-12-26 21:47:38 -07:00
memory_word_as_index.v
memory_word_as_index.ys
muxcover.ys muxcover: do not add decode muxes with x inputs 2023-01-26 05:19:45 +00:00
muxpack.v More deadname stuff 2021-06-09 12:40:33 +02:00
muxpack.ys
param_struct.ys
peepopt.ys peepopt: Fix padding for the peepopt_shiftmul_right pattern 2023-12-06 18:35:44 +01:00
peepopt_formal.ys peepopt clockgateff: add testcase 2024-08-07 10:21:52 +01:00
plugin.cc
plugin.sh tests: use yosys-config --datdir instead of hard-coded 2020-04-22 08:29:45 -07:00
pmgen_reduce.ys
pmux2shiftx.v
pmux2shiftx.ys Add #1135 testcase 2019-06-27 11:02:52 -07:00
port_sign_extend.v genrtlil: fix signed port connection codegen failures 2021-02-05 19:51:30 -05:00
port_sign_extend.ys
primitives.ys
printattr.ys
rand_const.sv
rand_const.ys
reg_wire_error.sv
reg_wire_error.ys
rename_scramble_name.ys
rtlil_signed_attribute.ys
rtlil_z_bits.ys
run-test.sh
scopeinfo.ys
scratchpad.ys add assert option to scratchpad command 2019-12-16 14:00:21 +01:00
script.ys
setundef.sv
setundef.ys Fix setting bits of parameters in setundef pass 2024-11-08 17:03:08 +01:00
sformatf.ys ast: use new format string helpers. 2023-08-11 04:46:52 +02:00
shregmap.v
shregmap.ys
signed.ys
signext.ys
sim_const.ys
specify.v verilog: ignore ranges too without -specify 2020-02-13 17:58:43 -08:00
specify.ys
src.ys verilog: add test 2020-03-11 06:51:03 -07:00
sta.ys
stat.ys create testcase to check correct addition of areas. 2025-04-20 16:44:22 +02:00
struct_access.sv Fix access to whole sub-structs (#3086) 2022-02-14 14:34:20 +01:00
struct_access.ys
sub.v
submod.ys
submod_extract.ys
sv_defines.ys
sv_defines_dup.ys
sv_defines_mismatch.ys Add support for SystemVerilog-style `define to Verilog frontend 2020-03-27 16:08:26 +00:00
sv_defines_too_few.ys
sv_implicit_ports.sh
svalways.sh
tcl_apis.tcl Redo integer passing on top of bignum 2024-12-02 19:56:51 +01:00
tcl_apis.v
tcl_apis.ys Fix test 2024-11-04 16:19:59 +01:00
wrapcell.ys
wreduce.ys
wreduce2.ys
write_gzip.ys
xaiger.ys