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18259 commits 138 branches 69 tags 63 MiB
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Author SHA1 Message Date
Stan Lee
d2e8f9b8a8 first round fixes 2026-01-20 21:45:13 -08:00
Robert O'Callahan
2c0448a81b Avoid spurious copy in IdStringCollector::trace_named() 2026-01-21 03:31:56 +00:00
github-actions[bot]
57ac113b7f Bump version 2026-01-21 00:27:51 +00:00
Stan Lee
29061d3051 leave no room for err 2026-01-20 15:55:05 -08:00
Stan Lee
45bd3f4515 change splitcells pass to remove some bracket from register names in blast mode 2026-01-20 15:50:43 -08:00
Stan Lee
60a81a2676 reg rename pass reads from vcd for original widths 2026-01-20 15:35:13 -08:00
Stan Lee
a5106da733 line reduction 2026-01-20 11:56:57 -08:00
Stan Lee
0ea4bb8a2d comment 2026-01-20 11:55:54 -08:00
Stan Lee
80364c608e significantly cleaner 2026-01-20 11:29:56 -08:00
Gus Smith
9ed56ac72c Mimic pattern of how other tests build plugins 
Seems like using --build isn't supported in CI
 2026-01-20 10:44:47 -08:00
Gus Smith
bd9dbea4ea Add -I 2026-01-20 10:07:44 -08:00
Gus Smith
0f6ef77775 Add test for ezCmdlineSAT 2026-01-20 09:28:00 -08:00
Gabriel Gouvine
979b673f20 ezsat: Fix handling of error codes 2026-01-20 07:54:50 -08:00
Gabriel Gouvine
d2b6bd00b1 ezsat: Rename files and class for ezCmdlineSat 2026-01-20 07:54:50 -08:00
Gabriel Gouvine
6565bf3ebf ezsat: Fix build for emscripten/wasi 2026-01-20 07:54:50 -08:00
Gabriel Gouvine
12315c0d17 ezsat: Support for assumptions in Sat command 2026-01-20 07:54:49 -08:00
Gabriel Gouvine
9315f02c17 ezsat: New Sat class to call an external command 2026-01-20 07:54:49 -08:00
Miodrag Milanović
bfd1401b32
Merge pull request #5612 from YosysHQ/sv2017 
verific: add explicit System Verilog 2017 option
 2026-01-20 14:44:46 +01:00
Miodrag Milanovic
d0fa4781c6 verific: Fix -sv2017 message and formatting 2026-01-20 08:07:26 +01:00
Gus Smith
491276983e Add test 2026-01-19 18:34:55 -08:00
Martin Povišer
90673cb0a2 techmap: Use -icells mode of frontend instead of type fixup 2026-01-19 16:49:49 -08:00
Martin Povišer
f67d4bcfa4 verilog: Do not set module_not_derived on internal cells 2026-01-19 16:48:13 -08:00
github-actions[bot]
49e5950791 Bump version 2026-01-20 00:26:10 +00:00
Stan Lee
c471014878 slightly cleaner 2026-01-19 12:58:36 -08:00
Stan Lee
6303eed1b4 works hierarchy 2026-01-19 12:22:22 -08:00
Stan Lee
186fc15f8f passes simple test 2026-01-19 12:10:48 -08:00
Stan Lee
e678e2a0c3 every step except wire connecting 2026-01-19 11:20:11 -08:00
Stan Lee
15026033a3 annotate original register width 2026-01-19 11:19:41 -08:00
Krystine Sherwin
0f478a5952
tests/bug5574: Fix for non threaded abc 2026-01-20 05:56:14 +13:00
Miodrag Milanovic
cc3038f468 verific: Fix -sv2017 message 2026-01-19 16:32:46 +01:00
Miodrag Milanović
2bde91b6ef
Merge pull request #5618 from YosysHQ/update_abc 
Update ABC as per 2026-01-19
 2026-01-19 15:45:02 +01:00
nella
67d10a41e8
Merge pull request #5617 from YosysHQ/emil/consteval-description 
consteval: describe
 2026-01-19 14:56:24 +01:00
Miodrag Milanovic
691983be14 Update ABC as per 2026-01-19 2026-01-19 12:08:24 +01:00
Emil J
7880f31acb
Merge pull request #5531 from YosysHQ/emil/shuffle-contributing-docs 
docs: shuffle and expand contributing info
 2026-01-19 12:02:49 +01:00
Emil J. Tywoniak
c3f36afe7f opt_balance_tree: mark experimental 2026-01-19 12:01:25 +01:00
Emil J. Tywoniak
befadf6d4d consteval: describe 2026-01-19 12:00:18 +01:00
Miodrag Milanović
9355fa5037
Merge pull request #5616 from rocallahan/fix-unused-var-warning 
Fix warning about unused variable in `dffunmap`.
 2026-01-19 08:24:48 +01:00
Robert O'Callahan
28c199fbbd Fix warning about unused variable in dffunmap. 2026-01-19 03:25:09 +00:00
Akash Levy
7792f0644a
Merge branch 'YosysHQ:main' into main 2026-01-18 17:17:45 -08:00
KrystalDelusion
8da8d681d0
Merge pull request #5544 from YosysHQ/krys/sim_check_eval_err 
Improve error handling in sim
 2026-01-19 09:51:12 +13:00
Natalia
b43c96b03d fix pyosys Design.run_pass binding to use Pass::call signature 2026-01-18 02:24:36 -08:00
Natalia
cf511628b0 modify generator for pyosys/wrappers.cc instead of headers 2026-01-18 02:11:09 -08:00
Stan Lee
4a1af73ec0 activity pass and a vcd writer bug fix 2026-01-16 16:32:04 -08:00
Miodrag Milanovic
d095d2c405 verific: add explicit System Verilog 2017 option 2026-01-16 07:56:53 +01:00
Natalia
ed64df737b Add -on/-off modes to debug pass 2026-01-15 12:07:26 -08:00
Akash Levy
33ddae41c3 Remove lut2bmux from silimate after upstreaming 2026-01-14 20:24:26 -08:00
Akash Levy
ef98c62bf2 Merge 2026-01-14 18:34:16 -08:00
Natalia
d5e1647d11 fix tests with truncation issues 2026-01-14 18:03:30 -08:00
Natalia
fb864e91ee Add Design::run_pass() API for programmatic pass execution 
This commit adds a new run_pass() method to the RTLIL::Design class,
providing a convenient API for executing Yosys passes programmatically.

This is particularly useful for PyYosys users who want to run passes
on a design object without needing to manually construct Pass::call()
invocations. The method wraps Pass::call() with appropriate logging
to maintain consistency with command-line pass execution.

Example usage (from Python):
    design = ys.Design()
    # ... build or load design ...
    design.run_pass("hierarchy")
    design.run_pass("proc")
    design.run_pass("opt")

Changes:
- kernel/rtlil.h: Add run_pass() method declaration
- kernel/rtlil.cc: Implement run_pass() method
- tests/unit/kernel/test_design_run_pass.cc: Add unit tests
 2026-01-14 17:35:45 -08:00
github-actions[bot]
967b47d984 Bump version 2026-01-15 00:24:54 +00:00