2876 commits

Author	SHA1	Message	Date
Eddie Hung	f7c0dbecee	abc9: fix abc9_arrival for flops	2020-02-13 12:34:09 -08:00
Eddie Hung	00d41905df	abc9: deprecate abc9_ff.init wire for (* abc9_init *) attr	2020-02-13 12:33:58 -08:00
Eddie Hung	c244b27b6d	abc9: cleanup	2020-02-10 10:17:23 -08:00
Eddie Hung	e6bb7b0782	Fix misc.abc9.abc9_abc9_luts	2020-02-07 08:27:45 -08:00
Eddie Hung	505557e93e	Merge pull request #1576 from YosysHQ/eddie/opt_merge_init ... opt_merge: discard \init of '$' cells with 'Q' port when merging	2020-02-05 14:56:26 -08:00
Eddie Hung	0b308c6835	abc9_ops: -reintegrate to use derived_type for box_ports	2020-02-05 14:46:48 -08:00
Eddie Hung	5ebdc0f8e0	Merge pull request #1638 from YosysHQ/eddie/fix1631 ... clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*	2020-02-05 19:31:18 +01:00
Eddie Hung	0671ae7d79	Merge pull request #1661 from YosysHQ/eddie/abc9_required ... abc9: add support for required times	2020-02-05 18:59:40 +01:00
Marcelina Kościelnicka	34d2fbd2f9	Add opt_lut_ins pass. (#1673)	2020-02-03 14:57:17 +01:00
David Shah	4bfd2ef4f3	sv: Improve handling of wildcard port connections ... Signed-off-by: David Shah <dave@ds0.me>	2020-02-02 16:12:33 +00:00
David Shah	7e741714df	hierarchy: Correct handling of wildcard port connections with default values ... Signed-off-by: David Shah <dave@ds0.me>	2020-02-02 16:12:33 +00:00
David Shah	5df591c023	hierarchy: Resolve SV wildcard port connections ... Signed-off-by: David Shah <dave@ds0.me>	2020-02-02 16:12:33 +00:00
David Shah	1055b6b1dd	Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonly ... synth_xilinx: add -dsp-multonly	2020-02-02 14:53:32 +00:00
David Shah	65716c9982	xilinx_dsp: Add multonly scratchpad var to bypass ... Signed-off-by: David Shah <dave@ds0.me>	2020-02-01 15:30:43 +00:00
Gabriel Somlo	8106c3d31b	abc9: restore ability to use ABCEXTERNAL ... Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>	2020-01-30 15:12:43 -05:00
Claire Wolf	1679682fa3	Merge branch 'vector_fix' of https://github.com/Kmanfi/yosys ... Also some minor fixes to the original PR.	2020-01-29 17:01:24 +01:00
Claire Wolf	4d0118d0c1	Merge pull request #1662 from YosysHQ/dave/opt-reduce-move-check ... opt_reduce: Call check() per run rather than per optimised cell	2020-01-29 15:27:11 +01:00
Eddie Hung	a855f23f22	Merge remote-tracking branch 'origin/master' into eddie/opt_merge_init	2020-01-28 12:46:18 -08:00
Eddie Hung	7939727d14	Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts ... Unpermute LUT ordering for ice40/ecp5/xilinx	2020-01-28 11:55:51 -08:00
Claire Wolf	4ddaa70fd6	Merge pull request #1567 from YosysHQ/eddie/sat_init_warning ... sat: suppress 'Warning: ignoring initial value on non-register: ...' when init[i] = 1'bx	2020-01-28 17:40:28 +01:00
N. Engelhardt	086c133ea5	Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate ... synth_xilinx: error out if tristate without '-iopad'	2020-01-28 17:24:54 +01:00
David Shah	6fd9cae5ca	opt_reduce: Call check() per run rather than per optimised cell ... Signed-off-by: David Shah <dave@ds0.me>	2020-01-28 09:42:01 +00:00
Pepijn de Vos	409e532433	redirect fuser stderr to /dev/null	2020-01-28 10:02:41 +01:00
Eddie Hung	21ce1b37fb	abc9_ops: -check for negative arrival/required times	2020-01-27 14:22:46 -08:00
Eddie Hung	e18aeda7ed	Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards ... Just like Verilog...	2020-01-27 14:02:13 -08:00
Eddie Hung	48f3f5213e	Merge pull request #1619 from YosysHQ/eddie/abc9_refactor ... Refactor `abc9` pass	2020-01-27 13:29:15 -08:00
Eddie Hung	f2576c096c	Merge branch 'eddie/abc9_refactor' into eddie/abc9_required	2020-01-27 12:29:28 -08:00
Eddie Hung	9009b76a69	abc9_ops: add comments	2020-01-27 11:18:21 -08:00
Eddie Hung	b178761551	ice40: reduce ABC9 internal fanout warnings with a param for CI->I3	2020-01-24 11:59:48 -08:00
Eddie Hung	dbf351390e	abc9: -reintegrate recover type from existing cell, check against boxid	2020-01-23 22:45:34 -08:00
Eddie Hung	245873d42d	abc9: warning message if no modules selected	2020-01-23 19:08:51 -08:00
Eddie Hung	f180dba753	abc9_ops: -prep_xaiger to skip (* keep *) cells	2020-01-23 18:56:06 -08:00
Eddie Hung	1d4314d888	abc9_ops -prep_dff: insert async s/r mux in holes when replacing $_DFF_*	2020-01-23 14:58:56 -08:00
Eddie Hung	af0e7637a2	alumacc: undo accidental commit	2020-01-22 20:54:03 -08:00
Eddie Hung	8eb5bb258c	Merge remote-tracking branch 'origin/eddie/abc9_fixes' into eddie/abc9_refactor	2020-01-22 12:30:14 -08:00
Eddie Hung	a94b41011d	abc9: error out if flip-flop init is 1'b1 for '-dff' ... Due to ABC sequential synthesis restriction	2020-01-22 10:08:48 -08:00
Eddie Hung	3b44b53e94	abc9: fix scratchpad entry abc9.verify	2020-01-22 09:36:54 -08:00
Eddie Hung	3d9737c1bd	Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor	2020-01-21 16:27:40 -08:00
Claire Wolf	5791c52e1b	Merge pull request #1637 from YosysHQ/mwk/fix-1634 ... fsm_detect: Add a cache to avoid excessive CPU usage for big mux networks.	2020-01-21 18:37:06 +01:00
Claire Wolf	f165a74824	Merge pull request #1621 from YosysHQ/clifford/fminit ... Add fminit pass	2020-01-20 22:01:57 +01:00
Eddie Hung	6a163b5ddd	xilinx_dsp: another typo; move xilinx specific test	2020-01-17 17:07:03 -08:00
Eddie Hung	db68e4c2a7	ice40_dsp: fix typo	2020-01-17 16:08:04 -08:00
Eddie Hung	e17f3f8c63	Consistency	2020-01-17 16:06:20 -08:00
Eddie Hung	ee500b6d8e	xilinx_dsp: add parameter defaults	2020-01-17 16:05:10 -08:00
Eddie Hung	4985318263	ice40_dsp: add default values for parameters	2020-01-17 15:37:52 -08:00
Eddie Hung	6692e5d558	ice40_dsp: tolerant of fanout-less outputs, as well as all-zero inputs	2020-01-17 15:28:02 -08:00
Eddie Hung	d4e188299b	abc9: add some log_{push,pop}() as per @nakengelhardt	2020-01-17 12:00:14 -08:00
Eddie Hung	5a63c19747	abc9_ops: -write_box is empty, output a dummy box to prevent ABC error	2020-01-15 13:14:48 -08:00
Eddie Hung	e30b6bbbf8	clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*	2020-01-15 09:51:31 -08:00
Eddie Hung	485e08e436	abc9_ops: cope with (* abc9_flop *) in place of (* abc9_box_id *)	2020-01-14 16:33:41 -08:00