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Merge branch 'eddie/abc9_refactor' into eddie/abc9_required

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This commit is contained in:
Eddie Hung 2020-01-27 12:29:28 -08:00
commit f2576c096c
26 changed files with 537 additions and 246 deletions
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26
passes/fsm/fsm_detect.cc
View file

@ -34,13 +34,20 @@ static SigSet<sig2driver_entry_t> sig2driver, sig2user;
static std::set<RTLIL::Cell*> muxtree_cells;
static SigPool sig_at_port;
static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, pool<Cell*> &recursion_monitor)
static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, pool<Cell*> &recursion_monitor, dict<RTLIL::SigSpec, bool> &mux_tree_cache)
{
if (mux_tree_cache.find(sig) != mux_tree_cache.end())
return mux_tree_cache.at(sig);
if (sig.is_fully_const() || old_sig == sig) {
ret_true:
mux_tree_cache[sig] = true;
return true;
}
if (sig_at_port.check_any(assign_map(sig))) {
ret_false:
mux_tree_cache[sig] = false;
return false;
}
@ -49,13 +56,13 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, poo
for (auto &cellport : cellport_list)
{
if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux") || cellport.second != "\\Y") {
return false;
goto ret_false;
}
if (recursion_monitor.count(cellport.first)) {
log_warning("logic loop in mux tree at signal %s in module %s.\n",
log_signal(sig), RTLIL::id2cstr(module->name));
return false;
goto ret_false;
}
recursion_monitor.insert(cellport.first);
@ -63,22 +70,22 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, poo
RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort("\\A"));
RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort("\\B"));
if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor)) {
if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor, mux_tree_cache)) {
recursion_monitor.erase(cellport.first);
return false;
goto ret_false;
}
for (int i = 0; i < sig_b.size(); i += sig_a.size())
if (!check_state_mux_tree(old_sig, sig_b.extract(i, sig_a.size()), recursion_monitor)) {
if (!check_state_mux_tree(old_sig, sig_b.extract(i, sig_a.size()), recursion_monitor, mux_tree_cache)) {
recursion_monitor.erase(cellport.first);
return false;
goto ret_false;
}
recursion_monitor.erase(cellport.first);
muxtree_cells.insert(cellport.first);
}
return true;
goto ret_true;
}
static bool check_state_users(RTLIL::SigSpec sig)
@ -143,11 +150,12 @@ static void detect_fsm(RTLIL::Wire *wire)
pool<Cell*> recursion_monitor;
RTLIL::SigSpec sig_q = assign_map(cellport.first->getPort("\\Q"));
RTLIL::SigSpec sig_d = assign_map(cellport.first->getPort("\\D"));
dict<RTLIL::SigSpec, bool> mux_tree_cache;
if (sig_q != assign_map(wire))
continue;
looks_like_state_reg = check_state_mux_tree(sig_q, sig_d, recursion_monitor);
looks_like_state_reg = check_state_mux_tree(sig_q, sig_d, recursion_monitor, mux_tree_cache);
looks_like_good_state_reg = check_state_users(sig_q);
if (!looks_like_state_reg)

8
passes/pmgen/ice40_dsp.cc
View file

@ -73,11 +73,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
// SB_MAC16 Input Interface
SigSpec A = st.sigA;
A.extend_u0(16, st.mul->getParam(ID(A_SIGNED)).as_bool());
A.extend_u0(16, st.mul->parameters.at(ID(A_SIGNED), State::S0).as_bool());
log_assert(GetSize(A) == 16);
SigSpec B = st.sigB;
B.extend_u0(16, st.mul->getParam(ID(B_SIGNED)).as_bool());
B.extend_u0(16, st.mul->parameters.at(ID(B_SIGNED), State::S0).as_bool());
log_assert(GetSize(B) == 16);
SigSpec CD = st.sigCD;
@ -248,8 +248,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
cell->setParam(ID(BOTADDSUB_CARRYSELECT), Const(0, 2));
cell->setParam(ID(MODE_8x8), State::S0);
cell->setParam(ID(A_SIGNED), st.mul->getParam(ID(A_SIGNED)).as_bool());
cell->setParam(ID(B_SIGNED), st.mul->getParam(ID(B_SIGNED)).as_bool());
cell->setParam(ID(A_SIGNED), st.mul->parameters.at(ID(A_SIGNED), State::S0).as_bool());
cell->setParam(ID(B_SIGNED), st.mul->parameters.at(ID(B_SIGNED), State::S0).as_bool());
if (st.ffO) {
if (st.o_lo)

21
passes/pmgen/ice40_dsp.pmg
View file

@ -56,11 +56,16 @@ code sigA sigB sigH
break;
sigH.append(O[i]);
}
// This sigM could have no users if downstream sinks (e.g. $add) is
// narrower than $mul result, for example
if (i == 0)
reject;
log_assert(nusers(O.extract_end(i)) <= 1);
endcode
code argQ ffA ffAholdmux ffArstmux ffAholdpol ffArstpol sigA clock clock_pol
if (mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()) {
if (mul->type != \SB_MAC16 || !param(mul, \A_REG, State::S0).as_bool()) {
argQ = sigA;
subpattern(in_dffe);
if (dff) {
@ -81,7 +86,7 @@ code argQ ffA ffAholdmux ffArstmux ffAholdpol ffArstpol sigA clock clock_pol
endcode
code argQ ffB ffBholdmux ffBrstmux ffBholdpol ffBrstpol sigB clock clock_pol
if (mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()) {
if (mul->type != \SB_MAC16 || !param(mul, \B_REG, State::S0).as_bool()) {
argQ = sigB;
subpattern(in_dffe);
if (dff) {
@ -104,7 +109,7 @@ endcode
code argD ffFJKG sigH clock clock_pol
if (nusers(sigH) == 2 &&
(mul->type != \SB_MAC16 ||
(!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool()))) {
(!param(mul, \TOP_8x8_MULT_REG, State::S0).as_bool() && !param(mul, \BOT_8x8_MULT_REG, State::S0).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1, State::S0).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1, State::S0).as_bool()))) {
argD = sigH;
subpattern(out_dffe);
if (dff) {
@ -143,7 +148,7 @@ endcode
code argD ffH sigH sigO clock clock_pol
if (ffFJKG && nusers(sigH) == 2 &&
(mul->type != \SB_MAC16 || !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())) {
(mul->type != \SB_MAC16 || !param(mul, \PIPELINE_16x16_MULT_REG2, State::S0).as_bool())) {
argD = sigH;
subpattern(out_dffe);
if (dff) {
@ -174,7 +179,7 @@ reject_ffH: ;
endcode
match add
if mul->type != \SB_MAC16 || (param(mul, \TOPOUTPUT_SELECT).as_int() == 3 && param(mul, \BOTOUTPUT_SELECT).as_int() == 3)
if mul->type != \SB_MAC16 || (param(mul, \TOPOUTPUT_SELECT, State::S0).as_int() == 3 && param(mul, \BOTOUTPUT_SELECT, State::S0).as_int() == 3)
select add->type.in($add)
choice <IdString> AB {\A, \B}
@ -200,7 +205,7 @@ code sigCD sigO cd_signed
if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
reject;
// If accumulator, check adder width and signedness
if (sigCD == sigH && (actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(add, \A_SIGNED).as_bool()))
if (sigCD == sigH && (actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED, State::S0).as_bool() != param(add, \A_SIGNED).as_bool()))
reject;
sigO = port(add, \Y);
@ -275,7 +280,7 @@ endcode
code argQ ffCD ffCDholdmux ffCDholdpol ffCDrstpol sigCD clock clock_pol
if (!sigCD.empty() && sigCD != sigO &&
(mul->type != \SB_MAC16 || (!param(mul, \C_REG).as_bool() && !param(mul, \D_REG).as_bool()))) {
(mul->type != \SB_MAC16 || (!param(mul, \C_REG, State::S0).as_bool() && !param(mul, \D_REG, State::S0).as_bool()))) {
argQ = sigCD;
subpattern(in_dffe);
if (dff) {
@ -328,6 +333,8 @@ arg argD argQ clock clock_pol
code
dff = nullptr;
if (argQ.empty())
reject;
for (auto c : argQ.chunks()) {
if (!c.wire)
reject;

16
passes/pmgen/xilinx_dsp.pmg
View file

@ -120,7 +120,7 @@ endcode
// reset functionality, using a subpattern discussed above)
// If matched, treat 'A' input as input of ADREG
code argQ ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol sigA clock
if (param(dsp, \ADREG).as_int() == 0) {
if (param(dsp, \ADREG, 1).as_int() == 0) {
argQ = sigA;
subpattern(in_dffe);
if (dff) {
@ -176,7 +176,7 @@ code argQ ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol sigA clock ffA2 ffA2cem
// Only search for ffA2 if there was a pre-adder
// (otherwise ffA2 would have been matched as ffAD)
if (preAdd) {
if (param(dsp, \AREG).as_int() == 0) {
if (param(dsp, \AREG, 1).as_int() == 0) {
argQ = sigA;
subpattern(in_dffe);
if (dff) {
@ -237,7 +237,7 @@ endcode
// (5) Match 'B' input for B2REG
// If B2REG, then match 'B' input for B1REG
code argQ ffB2 ffB2cemux ffB2rstmux ffB2cepol ffBrstpol sigB clock ffB1 ffB1cemux ffB1rstmux ffB1cepol
if (param(dsp, \BREG).as_int() == 0) {
if (param(dsp, \BREG, 1).as_int() == 0) {
argQ = sigB;
subpattern(in_dffe);
if (dff) {
@ -287,7 +287,7 @@ endcode
// (6) Match 'D' input for DREG
code argQ ffD ffDcemux ffDrstmux ffDcepol ffDrstpol sigD clock
if (param(dsp, \DREG).as_int() == 0) {
if (param(dsp, \DREG, 1).as_int() == 0) {
argQ = sigD;
subpattern(in_dffe);
if (dff) {
@ -308,7 +308,7 @@ endcode
// (7) Match 'P' output that exclusively drives an MREG
code argD ffM ffMcemux ffMrstmux ffMcepol ffMrstpol sigM sigP clock
if (param(dsp, \MREG).as_int() == 0 && nusers(sigM) == 2) {
if (param(dsp, \MREG, 1).as_int() == 0 && nusers(sigM) == 2) {
argD = sigM;
subpattern(out_dffe);
if (dff) {
@ -335,7 +335,7 @@ endcode
// recognised in xilinx_dsp.cc).
match postAdd
// Ensure that Z mux is not already used
if port(dsp, \OPMODE, SigSpec()).extract(4,3).is_fully_zero()
if port(dsp, \OPMODE, SigSpec(0, 7)).extract(4,3).is_fully_zero()
select postAdd->type.in($add)
select GetSize(port(postAdd, \Y)) <= 48
@ -363,7 +363,7 @@ endcode
// (9) Match 'P' output that exclusively drives a PREG
code argD ffP ffPcemux ffPrstmux ffPcepol ffPrstpol sigP clock
if (param(dsp, \PREG).as_int() == 0) {
if (param(dsp, \PREG, 1).as_int() == 0) {
int users = 2;
// If ffMcemux and no postAdd new-value net must have three users: ffMcemux, ffM and ffPcemux
if (ffMcemux && !postAdd) users++;
@ -460,7 +460,7 @@ arg argD argQ clock
code
dff = nullptr;
if (GetSize(argQ) == 0)
if (argQ.empty())
reject;
for (const auto &c : argQ.chunks()) {
// Abandon matches when 'Q' is a constant

1
passes/sat/Makefile.inc
View file

@ -12,4 +12,5 @@ OBJS += passes/sat/supercover.o
OBJS += passes/sat/fmcombine.o
OBJS += passes/sat/mutate.o
OBJS += passes/sat/cutpoint.o
OBJS += passes/sat/fminit.o

197
passes/sat/fminit.cc Normal file
View file

@ -0,0 +1,197 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct FminitPass : public Pass {
FminitPass() : Pass("fminit", "set init values/sequences for formal") { }
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" fminit [options] <selection>\n");
log("\n");
log("This pass creates init constraints (for example for reset sequences) in a formal\n");
log("model.\n");
log("\n");
log(" -seq <signal> <sequence>\n");
log(" Set sequence using comma-separated list of values, use 'z for\n");
log(" unconstrained bits. The last value is used for the remainder of the\n");
log(" trace.\n");
log("\n");
log(" -set <signal> <value>\n");
log(" Add constant value constraint\n");
log("\n");
log(" -posedge <signal>\n");
log(" -negedge <signal>\n");
log(" Set clock for init sequences\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
vector<pair<string, vector<string>>> initdata;
vector<pair<string, string>> setdata;
string clocksignal;
bool clockedge;
log_header(design, "Executing FMINIT pass.\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
// if (args[argidx] == "-o" && argidx+1 < args.size()) {
// filename = args[++argidx];
// continue;
// }
if (args[argidx] == "-seq" && argidx+2 < args.size()) {
string lhs = args[++argidx];
string rhs = args[++argidx];
initdata.push_back(make_pair(lhs, split_tokens(rhs, ",")));
continue;
}
if (args[argidx] == "-set" && argidx+2 < args.size()) {
string lhs = args[++argidx];
string rhs = args[++argidx];
setdata.push_back(make_pair(lhs, rhs));
continue;
}
if (args[argidx] == "-posedge" && argidx+1 < args.size()) {
clocksignal = args[++argidx];
clockedge = true;
continue;
}
if (args[argidx] == "-negedge" && argidx+1 < args.size()) {
clocksignal = args[++argidx];
clockedge = true;
continue;
}
break;
}
extra_args(args, argidx, design);
Module *module = nullptr;
for (auto mod : design->selected_modules()) {
if (module != nullptr)
log_error("'fminit' requires exactly one module to be selected.\n");
module = mod;
}
if (module == nullptr)
log_error("'fminit' requires exactly one module to be selected.\n");
SigSpec clksig;
if (!clocksignal.empty()) {
if (!SigSpec::parse(clksig, module, clocksignal))
log_error("Error parsing expression '%s'.\n", clocksignal.c_str());
}
for (auto &it : setdata)
{
SigSpec lhs, rhs;
if (!SigSpec::parse(lhs, module, it.first))
log_error("Error parsing expression '%s'.\n", it.first.c_str());
if (!SigSpec::parse_rhs(lhs, rhs, module, it.second))
log_error("Error parsing expression '%s'.\n", it.second.c_str());
SigSpec final_lhs, final_rhs;
for (int i = 0; i < GetSize(rhs); i++)
if (rhs[i] != State::Sz) {
final_lhs.append(lhs[i]);
final_rhs.append(rhs[i]);
}
if (!final_lhs.empty()) {
SigSpec eq = module->Eq(NEW_ID, final_lhs, final_rhs);
module->addAssume(NEW_ID, eq, State::S1);
}
}
vector<SigSpec> ctrlsig;
vector<SigSpec> ctrlsig_latched;
for (auto &it : initdata)
{
SigSpec lhs, rhs;
if (!SigSpec::parse(lhs, module, it.first))
log_error("Error parsing expression '%s'.\n", it.first.c_str());
for (int i = 0; i < GetSize(it.second); i++)
{
if (i >= GetSize(ctrlsig))
{
SigSpec insig = i > 0 ? ctrlsig.at(i-1) : State::S0;
Wire *outwire = module->addWire(NEW_ID);
outwire->attributes[ID(init)] = i > 0 ? State::S0 : State::S1;
if (clksig.empty())
module->addFf(NEW_ID, insig, outwire);
else
module->addDff(NEW_ID, clksig, insig, outwire, clockedge);
ctrlsig.push_back(outwire);
ctrlsig_latched.push_back(SigSpec());
}
if (i+1 == GetSize(it.second) && ctrlsig_latched[i].empty())
{
Wire *ffwire = module->addWire(NEW_ID);
ffwire->attributes[ID(init)] = State::S0;
SigSpec outsig = module->Or(NEW_ID, ffwire, ctrlsig[i]);
if (clksig.empty())
module->addFf(NEW_ID, outsig, ffwire);
else
module->addDff(NEW_ID, clksig, outsig, ffwire, clockedge);
ctrlsig_latched[i] = outsig;
}
SigSpec ctrl = i+1 == GetSize(it.second) ? ctrlsig_latched[i] : ctrlsig[i];
SigSpec final_lhs, final_rhs;
if (!SigSpec::parse_rhs(lhs, rhs, module, it.second[i]))
log_error("Error parsing expression '%s'.\n", it.second[i].c_str());
for (int i = 0; i < GetSize(rhs); i++)
if (rhs[i] != State::Sz) {
final_lhs.append(lhs[i]);
final_rhs.append(rhs[i]);
}
if (!final_lhs.empty()) {
SigSpec eq = module->Eq(NEW_ID, final_lhs, final_rhs);
module->addAssume(NEW_ID, eq, ctrl);
}
}
}
}
} FminitPass;
PRIVATE_NAMESPACE_END

11
passes/techmap/abc9.cc
View file

@ -240,9 +240,18 @@ struct Abc9Pass : public ScriptPass
}
extra_args(args, argidx, design);
log_assert(design);
if (design->selected_modules().empty()) {
log_warning("No modules selected for ABC9 techmapping.\n");
return;
}
log_header(design, "Executing ABC9 pass.\n");
log_push();
run_script(design, run_from, run_to);
log_pop();
}
void script() YS_OVERRIDE
@ -284,6 +293,7 @@ struct Abc9Pass : public ScriptPass
}
log_assert(!mod->attributes.count(ID(abc9_box_id)));
log_push();
active_design->selection().select(mod);
if (!active_design->selected_whole_module(mod))
@ -322,6 +332,7 @@ struct Abc9Pass : public ScriptPass
}
active_design->selection().selected_modules.clear();
log_pop();
}
active_design->selection_stack.pop_back();

8
passes/techmap/abc9_exe.cc
View file

@ -219,14 +219,14 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
for (size_t pos = abc9_script.find("{R}"); pos != std::string::npos; pos = abc9_script.find("{R}", pos))
abc9_script = abc9_script.substr(0, pos) + R + abc9_script.substr(pos+3);
abc9_script += stringf("; &ps -l; &write -n %s/output.aig;", tempdir_name.c_str());
abc9_script += stringf("; &ps -l; &write -n %s/output.aig", tempdir_name.c_str());
if (design->scratchpad_get_bool("abc9.verify")) {
if (dff_mode)
abc9_script += "verify -s;";
abc9_script += "; verify -s";
else
abc9_script += "verify;";
abc9_script += "; verify";
}
abc9_script += "time";
abc9_script += "; time";
abc9_script = add_echos_to_abc9_cmd(abc9_script);
for (size_t i = 0; i+1 < abc9_script.size(); i++)

180
passes/techmap/abc9_ops.cc
View file

@ -184,6 +184,8 @@ void prep_dff(RTLIL::Module *module)
SigSpec abc9_init = assign_map(abc9_init_wire);
if (!abc9_init.is_fully_const())
log_error("'%s.init' is not a constant wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
if (abc9_init == State::S1)
log_error("'%s.init' in module '%s' has value 1'b1 which is not supported by 'abc9 -dff'.\n", cell->name.c_str(), log_id(module));
r2 = cell->attributes.insert(std::make_pair(ID(abc9_init), abc9_init.as_const()));
log_assert(r2.second);
}
@ -193,38 +195,44 @@ void prep_dff(RTLIL::Module *module)
SigMap sigmap(holes_module);
dict<SigSpec, SigSpec> replace;
for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) {
auto cell = it->second;
if (cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
"$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_")) {
SigBit D = cell->getPort("\\D");
SigBit Q = cell->getPort("\\Q");
// Remove the $_DFF_* cell from what needs to be a combinatorial box
it = holes_module->cells_.erase(it);
Wire *port;
if (GetSize(Q.wire) == 1)
port = holes_module->wire(stringf("$abc%s", Q.wire->name.c_str()));
else
port = holes_module->wire(stringf("$abc%s[%d]", Q.wire->name.c_str(), Q.offset));
log_assert(port);
// Prepare to replace "assign <port> = $_DFF_*.Q;" with "assign <port> = $_DFF_*.D;"
// in order to extract just the combinatorial control logic that feeds the box
// (i.e. clock enable, synchronous reset, etc.)
replace.insert(std::make_pair(Q,D));
// Since `flatten` above would have created wires named "<cell>.Q",
// extract the pre-techmap cell name
auto pos = Q.wire->name.str().rfind(".");
log_assert(pos != std::string::npos);
IdString driver = Q.wire->name.substr(0, pos);
// And drive the signal that was previously driven by "DFF.Q" (typically
// used to implement clock-enable functionality) with the "<cell>.$abc9_currQ"
// wire (which itself is driven an by input port) we inserted above
Wire *currQ = holes_module->wire(stringf("%s.abc9_ff.Q", driver.c_str()));
log_assert(currQ);
holes_module->connect(Q, currQ);
}
for (auto cell : holes_module->cells().to_vector()) {
if (!cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
"$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_"))
continue;
SigBit D = cell->getPort("\\D");
SigBit Q = cell->getPort("\\Q");
// Emulate async control embedded inside $_DFF_* cell with mux in front of D
if (cell->type.in("$_DFF_NN0_", "$_DFF_PN0_"))
D = holes_module->MuxGate(NEW_ID, State::S0, D, cell->getPort("\\R"));
else if (cell->type.in("$_DFF_NN1_", "$_DFF_PN1_"))
D = holes_module->MuxGate(NEW_ID, State::S1, D, cell->getPort("\\R"));
else if (cell->type.in("$_DFF_NP0_", "$_DFF_PP0_"))
D = holes_module->MuxGate(NEW_ID, D, State::S0, cell->getPort("\\R"));
else if (cell->type.in("$_DFF_NP1_", "$_DFF_PP1_"))
D = holes_module->MuxGate(NEW_ID, D, State::S1, cell->getPort("\\R"));
// Remove the $_DFF_* cell from what needs to be a combinatorial box
holes_module->remove(cell);
Wire *port;
if (GetSize(Q.wire) == 1)
port = holes_module->wire(stringf("$abc%s", Q.wire->name.c_str()));
else
++it;
port = holes_module->wire(stringf("$abc%s[%d]", Q.wire->name.c_str(), Q.offset));
log_assert(port);
// Prepare to replace "assign <port> = $_DFF_*.Q;" with "assign <port> = $_DFF_*.D;"
// in order to extract just the combinatorial control logic that feeds the box
// (i.e. clock enable, synchronous reset, etc.)
replace.insert(std::make_pair(Q,D));
// Since `flatten` above would have created wires named "<cell>.Q",
// extract the pre-techmap cell name
auto pos = Q.wire->name.str().rfind(".");
log_assert(pos != std::string::npos);
IdString driver = Q.wire->name.substr(0, pos);
// And drive the signal that was previously driven by "DFF.Q" (typically
// used to implement clock-enable functionality) with the "<cell>.$abc9_currQ"
// wire (which itself is driven an by input port) we inserted above
Wire *currQ = holes_module->wire(stringf("%s.abc9_ff.Q", driver.c_str()));
log_assert(currQ);
holes_module->connect(Q, currQ);
}
for (auto &conn : holes_module->connections_)
@ -246,6 +254,8 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
for (auto cell : module->cells()) {
if (cell->type == "$__ABC9_FF_")
continue;
if (cell->has_keep_attr())
continue;
auto inst_module = module->design->module(cell->type);
bool abc9_flop = inst_module && inst_module->get_bool_attribute("\\abc9_flop");
@ -280,6 +290,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
else if (!yosys_celltypes.cell_known(cell->type))
continue;
// TODO: Speed up toposort -- we care about box ordering only
for (auto conn : cell->connections()) {
if (cell->input(conn.first))
for (auto bit : sigmap(conn.second))
@ -289,7 +300,6 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
for (auto bit : sigmap(conn.second))
bit_drivers[bit].insert(cell->name);
}
toposort.node(cell->name);
}
@ -589,6 +599,39 @@ void reintegrate(RTLIL::Module *module)
for (auto w : mapped_mod->wires())
module->addWire(remap_name(w->name), GetSize(w));
dict<IdString,std::vector<IdString>> box_ports;
for (auto m : design->modules()) {
if (!m->attributes.count(ID(abc9_box_id)))
continue;
auto r = box_ports.insert(m->name);
if (!r.second)
continue;
// Make carry in the last PI, and carry out the last PO
// since ABC requires it this way
IdString carry_in, carry_out;
for (const auto &port_name : m->ports) {
auto w = m->wire(port_name);
log_assert(w);
if (w->get_bool_attribute("\\abc9_carry")) {
log_assert(w->port_input != w->port_output);
if (w->port_input)
carry_in = port_name;
else if (w->port_output)
carry_out = port_name;
}
else
r.first->second.push_back(port_name);
}
if (carry_in != IdString()) {
r.first->second.push_back(carry_in);
r.first->second.push_back(carry_out);
}
}
std::vector<Cell*> boxes;
for (auto cell : module->cells().to_vector()) {
if (cell->has_keep_attr())
@ -604,10 +647,10 @@ void reintegrate(RTLIL::Module *module)
dict<RTLIL::Cell*,RTLIL::Cell*> not2drivers;
dict<SigBit, std::vector<RTLIL::Cell*>> bit2sinks;
dict<IdString,std::vector<IdString>> box_ports;
std::map<IdString, int> cell_stats;
for (auto mapped_cell : mapped_mod->cells())
{
// TODO: Speed up toposort -- we care about NOT ordering only
toposort.node(mapped_cell->name);
if (mapped_cell->type == ID($_NOT_)) {
@ -690,16 +733,8 @@ void reintegrate(RTLIL::Module *module)
RTLIL::Cell *existing_cell = module->cell(mapped_cell->name);
if (!existing_cell)
log_error("Cannot find existing box cell with name '%s' in original design.\n", log_id(mapped_cell));
#ifndef NDEBUG
RTLIL::Module* box_module = design->module(existing_cell->type);
IdString derived_type = box_module->derive(design, existing_cell->parameters);
RTLIL::Module* derived_module = design->module(derived_type);
log_assert(derived_module);
log_assert(mapped_cell->type == stringf("$__boxid%d", derived_module->attributes.at("\\abc9_box_id").as_int()));
#endif
mapped_cell->type = existing_cell->type;
if (mapped_cell->type == ID($__ABC9_DELAY)) {
if (existing_cell->type == ID($__ABC9_DELAY)) {
SigBit I = mapped_cell->getPort(ID(i));
SigBit O = mapped_cell->getPort(ID(o));
if (I.wire)
@ -710,19 +745,28 @@ void reintegrate(RTLIL::Module *module)
continue;
}
#ifndef NDEBUG
RTLIL::Module* box_module = design->module(existing_cell->type);
IdString derived_type = box_module->derive(design, existing_cell->parameters);
RTLIL::Module* derived_module = design->module(derived_type);
log_assert(derived_module);
log_assert(mapped_cell->type == stringf("$__boxid%d", derived_module->attributes.at("\\abc9_box_id").as_int()));
#endif
mapped_cell->type = existing_cell->type;
RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
cell->parameters = existing_cell->parameters;
cell->attributes = existing_cell->attributes;
module->swap_names(cell, existing_cell);
auto it = mapped_cell->connections_.find("\\i");
log_assert(it != mapped_cell->connections_.end());
SigSpec inputs = std::move(it->second);
mapped_cell->connections_.erase(it);
it = mapped_cell->connections_.find("\\o");
log_assert(it != mapped_cell->connections_.end());
SigSpec outputs = std::move(it->second);
mapped_cell->connections_.erase(it);
auto jt = mapped_cell->connections_.find("\\i");
log_assert(jt != mapped_cell->connections_.end());
SigSpec inputs = std::move(jt->second);
mapped_cell->connections_.erase(jt);
jt = mapped_cell->connections_.find("\\o");
log_assert(jt != mapped_cell->connections_.end());
SigSpec outputs = std::move(jt->second);
mapped_cell->connections_.erase(jt);
auto abc9_flop = box_module->attributes.count("\\abc9_flop");
if (!abc9_flop) {
@ -734,31 +778,6 @@ void reintegrate(RTLIL::Module *module)
bit_drivers[i].insert(mapped_cell->name);
}
auto r2 = box_ports.insert(cell->type);
if (r2.second) {
// Make carry in the last PI, and carry out the last PO
// since ABC requires it this way
IdString carry_in, carry_out;
for (const auto &port_name : box_module->ports) {
auto w = box_module->wire(port_name);
log_assert(w);
if (w->get_bool_attribute("\\abc9_carry")) {
log_assert(w->port_input != w->port_output);
if (w->port_input)
carry_in = port_name;
else if (w->port_output)
carry_out = port_name;
}
else
r2.first->second.push_back(port_name);
}
if (carry_in != IdString()) {
r2.first->second.push_back(carry_in);
r2.first->second.push_back(carry_out);
}
}
int input_count = 0, output_count = 0;
for (const auto &port_name : box_ports.at(cell->type)) {
RTLIL::Wire *w = box_module->wire(port_name);
@ -847,6 +866,17 @@ void reintegrate(RTLIL::Module *module)
}
}
// ABC9 will return $_NOT_ gates in its mapping (since they are
// treated as being "free"), in particular driving primary
// outputs (real primary outputs, or cells treated as blackboxes)
// or driving box inputs.
// Instead of just mapping those $_NOT_ gates into 2-input $lut-s
// at an area and delay cost, see if it is possible to push
// this $_NOT_ into the driving LUT, or into all sink LUTs.
// When this is not possible, (i.e. this signal drives two primary
// outputs, only one of which is complemented) and when the driver
// is a LUT, then clone the LUT so that it can be inverted without
// increasing depth/delay.
for (auto &it : bit_users)
if (bit_drivers.count(it.first))
for (auto driver_cell : bit_drivers.at(it.first))