mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 09:05:32 +00:00
Code Activity

sv: Improve handling of wildcard port connections

Browse source 
Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2019-11-22 15:07:55 +00:00
parent ebe1d7d5ab
commit 4bfd2ef4f3
3 changed files with 9 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

6
passes/hierarchy/hierarchy.cc
View file

@ -992,7 +992,7 @@ struct HierarchyPass : public Pass {
if (wire->port_input && wire->attributes.count("\\defaultvalue"))
defaults_db[module->name][wire->name] = wire->attributes.at("\\defaultvalue");
}
// Process SV implicit port connections
// Process SV implicit wildcard port connections
std::set<Module*> blackbox_derivatives;
std::vector<Module*> design_modules = design->modules();
@ -1000,7 +1000,7 @@ struct HierarchyPass : public Pass {
{
for (auto cell : module->cells())
{
if (!cell->get_bool_attribute(ID(implicit_port_conns)))
if (!cell->get_bool_attribute(ID(wildcard_port_conns)))
continue;
Module *m = design->module(cell->type);
@ -1042,7 +1042,7 @@ struct HierarchyPass : public Pass {
RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
cell->setPort(wire->name, parent_wire);
}
cell->attributes.erase(ID(implicit_port_conns));
cell->attributes.erase(ID(wildcard_port_conns));
}
}