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Code Activity
10410 commits 122 branches 59 tags 72 MiB
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1177 commits

Author SHA1 Message Date
whitequark
8262997c4e cxxrtl: fix typo in comment. NFC. 2020-06-08 12:50:35 +00:00
whitequark
fb3704c896 cxxrtl: minor debug-related improvements. 2020-06-08 12:50:35 +00:00
whitequark
ff5500f11a cxxrtl: rename cxxrtl.cc→cxxrtl_backend.cc. 
To avoid confusion with the C++ source files that are a part of
the simulation itself and not a part of Yosys build.
 2020-06-07 03:48:40 +00:00
whitequark
31f6c96b1f cxxrtl: add a C API for writing VCD dumps. 
This C API is fully featured.
 2020-06-07 03:48:00 +00:00
whitequark
68362a9053 cxxrtl: only write VCD values that were actually updated. 
On a representative design (Minerva SoC) this reduces VCD file size
by ~20× and runtime by ~3×.
 2020-06-07 03:48:00 +00:00
whitequark
9c36102669 cxxrtl: add a VCD writer using debug information. 2020-06-07 03:48:00 +00:00
whitequark
c399359ed6 cxxrtl: add a C API for driving and introspecting designs. 
Compared to the C++ API, the C API currently has two limitations:
  1. Memories cannot be updated in a race-free way.
  2. Black boxes cannot be implemented in C.
 2020-06-06 21:12:55 +00:00
whitequark
f6e16e7f4c cxxrtl: generate debug information for non-localized public wires. 
Debug information describes values, wires, and memories with a simple
C-compatible layout. It can be emitted on demand into a map, which
has no runtime cost when it is unused, and allows late bound designs.

The `hdlname` attribute is used as the lookup key such that original
names, as emitted by the frontend, can be used for debugging and
introspection.
 2020-06-06 21:12:55 +00:00
whitequark
784bfec67c
Merge pull request #2110 from BracketMaster/master 
MacOS has even stricter stack limits in catalina.
 2020-06-06 12:23:06 +00:00
whitequark
bd2ecc2dd3
Merge pull request #2113 from whitequark/cxxrtl-fix-sshr 
cxxrtl: fix implementation of $sshr cell
 2020-06-05 10:24:25 +00:00
N. Engelhardt
9669e0c7d5
Merge pull request #2109 from nakengelhardt/btor_internal_names 
btor backend: make not printing internal names default
 2020-06-05 11:36:08 +02:00
whitequark
025663adff cxxrtl: fix implementation of $sshr cell. 
Fixes #2111.
 2020-06-05 02:04:46 +00:00
Yehowshua Immanuel
da0778350b
more reasonable numbers for memory 2020-06-04 17:00:04 -04:00
Yehowshua Immanuel
5d29a9f633
MacOS has even stricter stack limits in catalina. 
Invoking sby in macOS Catalina fails because of bizarre stack limits in Catalina.
 2020-06-04 14:01:56 -04:00
Eddie Hung
69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve 
abc9: -dff improvements
 2020-06-04 08:15:25 -07:00
N. Engelhardt
82798ae575 btor backend: make not printing internal names default 2020-06-04 16:24:16 +02:00
Claire Wolf
5e8a9c61cd Add printf format attributes to btorf/infof helper functions 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-06-04 15:53:28 +02:00
N. Engelhardt
8ceb6686e0 btor backend: add option to not include internal names 2020-06-04 14:00:52 +02:00
whitequark
3bffd09d64
Merge pull request #2006 from jersey99/signed-in-rtlil-wire 
Preserve 'signed'-ness of a verilog wire through RTLIL
 2020-06-04 11:23:06 +00:00
Eddie Hung
45cd323055
Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes 
abc9: fixes around handling combinatorial loops
 2020-06-03 17:35:46 -07:00
clairexen
ea46ed81f9
Merge pull request #2018 from boqwxp/qbfsat-timeout 
smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4.
 2020-05-30 15:04:51 +02:00
Alberto Gonzalez
ea30465107
smtbmc: Remove superfluous yosys-smt2-timeout file macro. 
Co-Authored-By: clairexen <claire@symbioticeda.com>
 2020-05-29 21:33:00 +00:00
clairexen
94c1035389
Merge pull request #1885 from Xiretza/mod-rem-cells 
Fix modulo/remainder semantics
 2020-05-29 16:37:23 +02:00
clairexen
1c8d5a08a0
Merge pull request #2016 from boqwxp/qbfsat-yices 
qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices the default.
 2020-05-29 16:21:45 +02:00
Xiretza
edd8ff2c07
Add flooring division operator 
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.

This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
 2020-05-28 22:59:04 +02:00
Xiretza
17163cf43a
Add flooring modulo operator 
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).

This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
 2020-05-28 22:59:03 +02:00
whitequark
736ccb2ad5
Merge pull request #2031 from epfl-vlsc/master 
Add extmodule support to firrtl backend
 2020-05-28 09:59:17 +00:00
whitequark
2974183855
Merge pull request #2063 from boqwxp/techmapped-firrtl 
firrtl: Accept techmapped cell types in FIRRTL backend.
 2020-05-28 09:42:58 +00:00
whitequark
0bf6b164be cxxrtl: make logging a little bit nicer. 2020-05-26 21:37:32 +00:00
whitequark
e9c07e2bda cxxrtl: add missing parts of commit 281c9685. 2020-05-26 21:34:20 +00:00
Eddie Hung
1826370b3a xaiger: promote abc9_keep wires 2020-05-25 16:40:30 -07:00
Alberto Gonzalez
9847a4eea8
smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4. 2020-05-25 20:39:30 +00:00
Alberto Gonzalez
54570a3978
qbfsat: Move SMT2 info statements back to the top of the file. 2020-05-25 20:38:29 +00:00
Alberto Gonzalez
903456c267
qbfsat: Add -solver option and allow choice of Z3 or Yices, making Yices the default. 
Ensures that "BV" is the logic whenever solving an exists-forall problem with Yices, moves the "(set-logic ...)" directive above any non-info line, sets the `ef-max-iters` parameter to a very high number when using Yices in exists-forall mode so as not to prematurely abandon difficult problems, and does not provide the incompatible "--incremental" Yices argument when in exists-forall mode.
 2020-05-25 20:38:29 +00:00
Eddie Hung
9e6c288e5a xaiger: cleanup 2020-05-25 08:43:33 -07:00
Eddie Hung
d64df21630 xaiger: do not derive cells 2020-05-24 08:17:30 -07:00
whitequark
281c96856a cxxrtl: get rid of -O5 aka opt_clean -purge optimization level. 
This isn't actually necessary anymore after scheduling was improved,
and `clean -purge` disrupts the mapping between wires in the input
RTLIL netlist and the output CXXRTL code.
 2020-05-22 19:08:30 +00:00
N. Engelhardt
7c4e580f8f
Merge pull request #2054 from boqwxp/fix-smtbmc 
smtbmc: Fix return status handling.
 2020-05-20 08:55:36 +02:00
Alberto Gonzalez
1053032a81
smtbmc: Fix typo in error message. 
Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
 2020-05-19 16:13:44 +00:00
Alberto Gonzalez
049e4caceb
firrtl: Accept techmapped cell types in FIRRTL backend. 2020-05-17 10:03:11 +00:00
Eddie Hung
67fc0c3698 abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_ 
instead of moving them to $__ prefix
 2020-05-14 16:44:35 -07:00
Eddie Hung
97a0a04314 abc9_ops/xaiger: further reducing Module::derive() calls by ... 
replacing _all_ (* abc9_box *) instantiations with their derived types
 2020-05-14 10:33:57 -07:00
Eddie Hung
e79127fceb Cleanup; reduce Module::derive() calls 2020-05-14 10:33:57 -07:00
Eddie Hung
e357b40e7a xaiger: no longer use nonstandard even/odd to designate +ve/-ve polarity 2020-05-14 10:33:56 -07:00
Eddie Hung
722540dbf9 abc9: not enough to techmap_fail on (* init=1 *), hide them using $__ 2020-05-14 10:33:56 -07:00
Eddie Hung
63246a5c0e Revert "Merge pull request #1917 from YosysHQ/eddie/abc9_delay_check" 
This reverts commit 759283fa65, reversing
changes made to f41c7ccfff.
 2020-05-14 10:33:56 -07:00
Eddie Hung
4c6647a469 xaiger: always sort input/output bits by port id 
redundant for normal design, but necessary for holes
 2020-05-14 10:33:56 -07:00
Eddie Hung
ec4bbb1444 abc9: generate $abc9_holes design instead of <name>$holes 2020-05-14 10:33:56 -07:00
Eddie Hung
6f4f795953 aiger/xaiger: use odd for negedge clk, even for posedge 
Since abc9 doesn't like negative mergeability values
 2020-05-14 10:33:56 -07:00
Eddie Hung
f975cf39cb xaiger: update help text 2020-05-14 10:33:56 -07:00