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Merge pull request #2006 from jersey99/signed-in-rtlil-wire

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Preserve 'signed'-ness of a verilog wire through RTLIL
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whitequark 2020-06-04 11:23:06 +00:00 • committed by GitHub
commit 3bffd09d64
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7 changed files with 19 additions and 2 deletions
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2
backends/ilang/ilang_backend.cc
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@ -131,6 +131,8 @@ void ILANG_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::
f << stringf("output %d ", wire->port_id);
if (wire->port_input && wire->port_output)
f << stringf("inout %d ", wire->port_id);
if (wire->is_signed)
f << stringf("signed ");
f << stringf("%s\n", wire->name.c_str());
}

4
backends/json/json.cc
View file

@ -160,6 +160,8 @@ struct JsonWriter
f << stringf(" \"offset\": %d,\n", w->start_offset);
if (w->upto)
f << stringf(" \"upto\": 1,\n");
if (w->is_signed)
f << stringf(" \"signed\": %d,\n", w->is_signed);
f << stringf(" \"bits\": %s\n", get_bits(w).c_str());
f << stringf(" }");
first = false;
@ -227,6 +229,8 @@ struct JsonWriter
f << stringf(" \"offset\": %d,\n", w->start_offset);
if (w->upto)
f << stringf(" \"upto\": 1,\n");
if (w->is_signed)
f << stringf(" \"signed\": %d,\n", w->is_signed);
f << stringf(" \"attributes\": {");
write_parameters(w->attributes);
f << stringf("\n }\n");