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abc9: generate $abc9_holes design instead of <name>$holes
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parent
c52bb11fb6
commit
ec4bbb1444
3 changed files with 28 additions and 18 deletions
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@ -676,7 +676,13 @@ struct XAigerWriter
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
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RTLIL::Design *holes_design;
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auto it = saved_designs.find("$abc9_holes");
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if (it != saved_designs.end())
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holes_design = it->second;
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else
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holes_design = nullptr;
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RTLIL::Module *holes_module = holes_design ? holes_design->module(module->name) : nullptr;
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if (holes_module) {
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std::stringstream a_buffer;
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XAigerWriter writer(holes_module, false /* dff_mode */, true /* holes_mode */);
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@ -768,8 +774,8 @@ struct XAigerBackend : public Backend {
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log("Write the top module (according to the (* top *) attribute or if only one module\n");
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log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, (optionally\n");
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log("$_DFF_N_, $_DFF_P_), or non (* abc9_box *) cells will be converted into psuedo-\n");
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log("inputs and pseudo-outputs. Whitebox contents will be taken from the\n");
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log("'<module-name>$holes' module, if it exists.\n");
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log("inputs and pseudo-outputs. Whitebox contents will be taken from the equivalent\n");
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log("module in the '$abc9_holes' design, if it exists.\n");
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log("\n");
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log(" -ascii\n");
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log(" write ASCII version of AIGER format\n");
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