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cxxrtl: add missing parts of commit 281c9685
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59b355fb85
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e9c07e2bda
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@ -513,7 +513,6 @@ struct CxxrtlWorker {
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bool elide_public = false;
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bool localize_internal = false;
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bool localize_public = false;
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bool run_opt_clean_purge = false;
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bool run_proc_flatten = false;
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bool max_opt_level = false;
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@ -2046,7 +2045,7 @@ struct CxxrtlWorker {
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}
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if (has_feedback_arcs || has_buffered_wires) {
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// Although both non-feedback buffered combinatorial wires and apparent feedback wires may be eliminated
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// by optimizing the design, if after `opt_clean -purge` there are any feedback wires remaining, it is very
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// by optimizing the design, if after `proc; flatten` there are any feedback wires remaining, it is very
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// likely that these feedback wires are indicative of a true logic loop, so they get emphasized in the message.
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const char *why_pessimistic = nullptr;
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if (has_feedback_arcs)
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@ -2106,15 +2105,13 @@ struct CxxrtlWorker {
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if (has_sync_init || has_packed_mem)
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check_design(design, has_sync_init, has_packed_mem);
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log_assert(!(has_sync_init || has_packed_mem));
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if (run_opt_clean_purge)
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Pass::call(design, "opt_clean -purge");
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log_pop();
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analyze_design(design);
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}
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};
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struct CxxrtlBackend : public Backend {
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static const int DEFAULT_OPT_LEVEL = 6;
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static const int DEFAULT_OPT_LEVEL = 5;
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CxxrtlBackend() : Backend("cxxrtl", "convert design to C++ RTL simulation") { }
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void help() YS_OVERRIDE
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@ -2340,6 +2337,7 @@ struct CxxrtlBackend : public Backend {
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extra_args(f, filename, args, argidx);
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switch (opt_level) {
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// the highest level here must match DEFAULT_OPT_LEVEL
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case 5:
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worker.max_opt_level = true;
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worker.run_proc_flatten = true;
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