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Author	SHA1	Message	Date
Miodrag Milanović	f624bcf2db	Merge pull request #5990 from YosysHQ/self_sanitizer ... Self hosted sanitizer	2026-06-26 15:39:54 +00:00
Miodrag Milanovic	cd4198e024	Skip this step during merge queue since we have already run those	2026-06-26 17:17:35 +02:00
Miodrag Milanovic	0c13257915	Sanitizer self hosted	2026-06-26 17:10:44 +02:00
Miodrag Milanović	6cee0af8ad	Merge pull request #5989 from YosysHQ/ccache2 ... Store caches on main	2026-06-26 13:15:55 +00:00
Miodrag Milanovic	8ad1b7f2b2	Remove nix parameter	2026-06-26 14:35:54 +02:00
Miodrag Milanovic	84248a008b	Bump minimal clang to 16	2026-06-26 14:35:44 +02:00
Miodrag Milanovic	459a933005	Store caches on main	2026-06-26 14:33:12 +02:00
Miodrag Milanović	baed9c4185	Merge pull request #5987 from YosysHQ/update_abc ... Update ABC as per 2026-06-25	2026-06-26 10:44:01 +00:00
Miodrag Milanović	0af18fa273	Merge pull request #5988 from YosysHQ/ccache ... CI cleanups and improvements	2026-06-26 09:13:43 +00:00
Miodrag Milanovic	cefe7266b1	Add restore keys	2026-06-26 10:55:28 +02:00
Miodrag Milanovic	bd1cb398e4	Update iverilog and build-env	2026-06-26 10:11:15 +02:00
Miodrag Milanovic	18902ddd34	Fix formatting	2026-06-26 08:11:16 +02:00
Miodrag Milanovic	53138724db	Remove intel macOS compiler	2026-06-26 08:09:10 +02:00
Miodrag Milanovic	f1820e4423	Use updated msvc-dev-cmd action	2026-06-26 08:08:53 +02:00
Miodrag Milanovic	b8459c9dec	Use forked skip-duplicate-actions	2026-06-26 08:08:22 +02:00
Miodrag Milanovic	3f4fa079f8	Upgrade base github actions	2026-06-26 08:06:44 +02:00
Miodrag Milanovic	63dd0e1a60	Add ccache	2026-06-26 08:02:58 +02:00
Miodrag Milanovic	06a64af1f4	Set CodeQL to be executed weekly	2026-06-26 07:56:30 +02:00
Miodrag Milanovic	2bc5aa5cf4	Update ABC as per 2026-06-25	2026-06-25 14:20:27 +02:00
Miodrag Milanović	23aadd92ab	Merge pull request #5985 from YosysHQ/logid_left ... Remove leftover use of log_id	2026-06-24 07:15:32 +00:00
Miodrag Milanovic	fd3ec58055	Remove leftover use of log_id	2026-06-24 08:04:48 +02:00
KrystalDelusion	a07c484ce1	Merge pull request #5981 from YosysHQ/krys/equiv_opt_unknown ... equiv_opt: Add ignore-unknown-cells	2026-06-23 19:58:30 +00:00
Miodrag Milanović	30d0b39a15	Merge pull request #5982 from YosysHQ/cleanup ... File cleanup	2026-06-23 14:07:10 +00:00
Miodrag Milanovic	43d8a84bdc	Add pre-commit config file	2026-06-23 07:30:54 +02:00
Miodrag Milanovic	55034dbe91	Remaining fix	2026-06-23 07:26:12 +02:00
Miodrag Milanovic	a689342207	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
Miodrag Milanovic	48a3dcc02a	End of file fix	2026-06-23 07:23:41 +02:00
Miodrag Milanovic	3ac58b3ac1	Fixed line endings	2026-06-23 07:17:22 +02:00
Miodrag Milanovic	1f0ac8fffc	Remove utf-8 marker	2026-06-23 07:14:20 +02:00
Miodrag Milanovic	f362e1db0e	Remove executable flag from .v files	2026-06-23 07:12:43 +02:00
KrystalDelusion	fe8f29b5f8	Merge pull request #5975 from dobios/patch-1 ... [docs] nit: least/most significant bits referred to using LSB/MSB instead of LSb/MSb	2026-06-22 23:21:34 +00:00
KrystalDelusion	e20a9168fb	Merge pull request #5971 from YosysHQ/krys/upto_indexing ... write_verilog: Fix upto indexing for single bit	2026-06-22 23:04:16 +00:00
Krystine Sherwin	de6aa77dc8	equiv_opt: Add ignore-unknown-cells	2026-06-23 10:54:00 +12:00
Miodrag Milanović	0bd04dbae3	Merge pull request #5980 from YosysHQ/synth_intel ... synth_intel: fix broken dsp mapping	2026-06-22 16:46:02 +00:00
Miodrag Milanovic	09eef69e31	synth_intel: fix broken dsp mapping	2026-06-22 17:51:26 +02:00
Miodrag Milanović	6edbcecc52	Merge pull request #5972 from YosysHQ/ci_mingw64 ... Add mingw64 build to CI	2026-06-22 14:54:56 +00:00
Miodrag Milanović	9139c94c8c	Merge pull request #5977 from YosysHQ/bitwuzla ... smtbmc: support latest bitwuzla	2026-06-22 14:23:35 +00:00
Miodrag Milanovic	ed654de3d9	Add mingw64 build to CI	2026-06-22 16:22:13 +02:00
nella	57ec784983	Merge pull request #5953 from YosysHQ/nella/muxcover-enhancements ... Add muxcover x peepopt regression test (#964).	2026-06-22 10:13:43 +00:00
nella	8f5d2d5894	Use -assert-none.	2026-06-22 11:12:00 +02:00
nella	3d0c868af0	Merge pull request #5952 from YosysHQ/nella/vector-index ... Optimize upto vector indexing (Fix #892).	2026-06-22 09:05:26 +00:00
nella	6ffc938a75	Merge pull request #5701 from YosysHQ/gus/sim-with-vcd-tuneup ... Add warnings and errors to `sim -r` with VCD code path	2026-06-22 09:02:32 +00:00
Miodrag Milanović	f699624abf	Merge pull request #5978 from YosysHQ/remove_def ... Remove define since snprintf is supported in MSVC now	2026-06-22 08:49:26 +00:00
Miodrag Milanovic	94e43f7675	Remove define since snprintf is supported in MSVC now	2026-06-22 09:50:39 +02:00
Miodrag Milanovic	ebcbc06951	smtbmc: support latest bitwuzla	2026-06-22 08:40:16 +02:00
Amelia Dobis	41566a6b70	more typo found	2026-06-19 17:47:39 -04:00
Amelia Dobis	54d43d85e3	[docs] nit: usign the right acronym to refer to the right thing ... Tiny nit, but the description of `RTLIL::Wire` was using MSB and LSB to refer to the least and most significant *bits* of a wire and not Bytes, which should be referred to using LSb and MSb instead	2026-06-19 17:30:28 -04:00
Krystine Sherwin	b77bb851ed	tests: Add mixed_upto write_verilog test	2026-06-19 11:20:01 +12:00
Krystine Sherwin	338d4adef2	write_verilog: Fix upto indexing for single bit	2026-06-19 10:18:27 +12:00
nella	5d7486115a	Merge pull request #5887 from YosysHQ/nella/fix-signedness-4402 ... Fix: `read_verilog` doesn't respect `signed` keyword	2026-06-18 16:53:37 +00:00