mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-06-26 10:38:47 +00:00
Code Activity

more typo found

Browse source
This commit is contained in:
Amelia Dobis 2026-06-19 17:47:39 -04:00 • committed by GitHub
parent 54d43d85e3
commit 41566a6b70
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
1 changed files with 2 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

4
docs/source/yosys_internals/formats/rtlil_rep.rst
View file

@ -171,8 +171,8 @@ signals. This makes some aspects of RTLIL more complex but enables Yosys to be
used for coarse grain synthesis where the cells of the target architecture
operate on entire signal vectors instead of single bit wires.
In Verilog and VHDL, busses may have arbitrary bounds, and LSB can have either
the lowest or the highest bit index. In RTLIL, bit 0 always corresponds to LSB;
In Verilog and VHDL, busses may have arbitrary bounds, and LSb can have either
the lowest or the highest bit index. In RTLIL, bit 0 always corresponds to LSb;
however, information from the HDL frontend is preserved so that the bus will be
correctly indexed in error messages, backend output, constraint files, etc.