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write_verilog: Fix upto indexing for single bit

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Krystine Sherwin 2026-06-19 10:18:27 +12:00
parent 2195277b5a
commit 338d4adef2
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1 changed files with 15 additions and 7 deletions
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22
backends/verilog/verilog_backend.cc
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@ -197,14 +197,22 @@ bool is_reg_wire(RTLIL::SigSpec sig, std::string &reg_name)
reg_name = id(chunk.wire->name);
if (sig.size() != chunk.wire->width) {
if (sig.size() == 1)
reg_name += stringf("[%d]", chunk.wire->start_offset + chunk.offset);
else if (chunk.wire->upto)
reg_name += stringf("[%d:%d]", (chunk.wire->width - (chunk.offset + chunk.width - 1) - 1) + chunk.wire->start_offset,
(chunk.wire->width - chunk.offset - 1) + chunk.wire->start_offset);
int idx;
if (chunk.wire->upto)
idx = (chunk.wire->width - chunk.offset - 1) + chunk.wire->start_offset;
else
reg_name += stringf("[%d:%d]", chunk.wire->start_offset + chunk.offset + chunk.width - 1,
chunk.wire->start_offset + chunk.offset);
idx = chunk.wire->start_offset + chunk.offset;
if (sig.size() == 1)
reg_name += stringf("[%d]", idx);
else {
int left_idx;
if (chunk.wire->upto)
left_idx = (chunk.wire->width - (chunk.offset + chunk.width - 1) - 1) + chunk.wire->start_offset;
else
left_idx = chunk.wire->start_offset + chunk.offset + chunk.width - 1;
reg_name += stringf("[%d:%d]", left_idx, idx);
}
}
return true;